KMAC/MASKED Simulation Results

Sunday October 26 2025 00:06:53 UTC

GitHub Revision: 06d697f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.877m	7.749ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.790s	64.327us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.570s	81.789us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	12.890s	8.058ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.770s	5.984ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.730s	34.823us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.570s	81.789us	20	20	100.00
		kmac_csr_aliasing	7.770s	5.984ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.230s	21.182us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.840s	155.940us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.049h	808.978ms	50	50	100.00
V2	burst_write	kmac_burst_write	23.421m	71.768ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	37.864m	63.184ms	5	5	100.00
		kmac_test_vectors_sha3_256	25.517m	117.969ms	5	5	100.00
		kmac_test_vectors_sha3_384	28.436m	94.514ms	5	5	100.00
		kmac_test_vectors_sha3_512	19.392m	40.755ms	5	5	100.00
		kmac_test_vectors_shake_128	38.785m	70.994ms	5	5	100.00
		kmac_test_vectors_shake_256	38.615m	174.531ms	5	5	100.00
		kmac_test_vectors_kmac	3.430s	377.468us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.920s	451.591us	5	5	100.00
V2	sideload	kmac_sideload	8.739m	144.927ms	50	50	100.00
V2	app	kmac_app	6.809m	38.420ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.405m	27.050ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.761m	94.892ms	50	50	100.00
V2	error	kmac_error	7.694m	27.560ms	49	50	98.00
V2	key_error	kmac_key_error	19.950s	16.122ms	49	50	98.00
V2	sideload_invalid	kmac_sideload_invalid	9.720s	1.008ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	39.190s	3.429ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	27.230s	1.257ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.055m	6.839ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	42.360s	1.934ms	50	50	100.00
V2	stress_all	kmac_stress_all	38.952m	287.034ms	49	50	98.00
V2	intr_test	kmac_intr_test	1.450s	84.394us	50	50	100.00
V2	alert_test	kmac_alert_test	1.280s	24.842us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.340s	74.245us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.340s	74.245us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.790s	64.327us	5	5	100.00
		kmac_csr_rw	1.570s	81.789us	20	20	100.00
		kmac_csr_aliasing	7.770s	5.984ms	5	5	100.00
		kmac_same_csr_outstanding	2.780s	492.636us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.790s	64.327us	5	5	100.00
		kmac_csr_rw	1.570s	81.789us	20	20	100.00
		kmac_csr_aliasing	7.770s	5.984ms	5	5	100.00
		kmac_same_csr_outstanding	2.780s	492.636us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.460s	629.797us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.460s	629.797us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.460s	629.797us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.460s	629.797us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.410s	1.042ms	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.692m	19.014ms	5	5	100.00
		kmac_tl_intg_err	3.980s	188.397us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.980s	188.397us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	42.360s	1.934ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.877m	7.749ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.739m	144.927ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.460s	629.797us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.692m	19.014ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.692m	19.014ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.692m	19.014ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.877m	7.749ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	42.360s	1.934ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.692m	19.014ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.223m	6.371ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.877m	7.749ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.901m	24.213ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			935	940	99.47

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.93	99.20	94.45	99.89	78.17	97.08	97.83	97.86

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 3.kmac_shadow_reg_errors_with_csr_rw.75826502498578628832859303915268268487820105194937655446936682898023243786656
      Line 468, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_ERROR @  85333768 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (3276308489 [0xc3488009] vs 0 [0x0]) Regname: kmac_reg_block.prefix_8.prefix_0 reset value: 0x0
        UVM_INFO @  85333768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 8.kmac_stress_all_with_rand_reset.23772425061077237316850929549850331593032150354939828809241425190139160776119
      Line 351, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4504554505 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 4504554505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.err_code reset value: * has 1 failures:

  • Test kmac_key_error has 1 failures.

    • 16.kmac_key_error.58114765539890962567072830500133435937882937854118378775168225332770422817854
      Line 74, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_key_error/latest/run.log

        UVM_ERROR @   4602257 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 16777216 [0x1000000]) Regname: kmac_reg_block.err_code reset value: 0x0
        UVM_INFO @   4602257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:

  • Test kmac_stress_all has 1 failures.

    • 16.kmac_stress_all.15235403311993106540221349661340174248703491577261847930002144582362826091923
      Line 89, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_stress_all/latest/run.log

        UVM_ERROR @ 216042275 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @ 216042275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test kmac_error has 1 failures.

    • 26.kmac_error.37415592698374650389260718880071092463323923810384520781431000419149543908510
      Line 209, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/26.kmac_error/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---