KMAC/UNMASKED Simulation Results

Sunday October 26 2025 00:06:53 UTC

GitHub Revision: 06d697f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.242m	8.394ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.400s	30.064us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.580s	451.434us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	14.820s	289.373us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.130s	269.727us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.920s	86.498us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.580s	451.434us	20	20	100.00
		kmac_csr_aliasing	8.130s	269.727us	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.080s	16.317us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.880s	36.718us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	55.603m	1.803s	50	50	100.00
V2	burst_write	kmac_burst_write	15.615m	33.717ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	31.372m	94.153ms	5	5	100.00
		kmac_test_vectors_sha3_256	26.797m	61.269ms	5	5	100.00
		kmac_test_vectors_sha3_384	22.550m	582.373ms	5	5	100.00
		kmac_test_vectors_sha3_512	15.402m	32.411ms	5	5	100.00
		kmac_test_vectors_shake_128	36.334m	107.534ms	5	5	100.00
		kmac_test_vectors_shake_256	6.097m	47.779ms	5	5	100.00
		kmac_test_vectors_kmac	2.560s	85.259us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.010s	110.081us	5	5	100.00
V2	sideload	kmac_sideload	6.371m	169.864ms	50	50	100.00
V2	app	kmac_app	5.269m	55.514ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.432m	14.693ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.303m	77.522ms	50	50	100.00
V2	error	kmac_error	6.787m	15.549ms	50	50	100.00
V2	key_error	kmac_key_error	17.020s	19.280ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.281m	10.020ms	43	50	86.00
V2	edn_timeout_error	kmac_edn_timeout_error	35.620s	19.831ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	33.760s	4.375ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	53.820s	27.936ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	44.110s	958.944us	50	50	100.00
V2	stress_all	kmac_stress_all	23.917m	89.144ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.170s	19.921us	50	50	100.00
V2	alert_test	kmac_alert_test	1.280s	37.990us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.270s	2.341ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.270s	2.341ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.400s	30.064us	5	5	100.00
		kmac_csr_rw	1.580s	451.434us	20	20	100.00
		kmac_csr_aliasing	8.130s	269.727us	5	5	100.00
		kmac_same_csr_outstanding	3.280s	249.796us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.400s	30.064us	5	5	100.00
		kmac_csr_rw	1.580s	451.434us	20	20	100.00
		kmac_csr_aliasing	8.130s	269.727us	5	5	100.00
		kmac_same_csr_outstanding	3.280s	249.796us	20	20	100.00
V2		TOTAL			733	740	99.05
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.680s	161.095us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.680s	161.095us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.680s	161.095us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.680s	161.095us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.210s	210.000us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.310m	9.783ms	5	5	100.00
		kmac_tl_intg_err	6.000s	430.489us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.000s	430.489us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	44.110s	958.944us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.242m	8.394ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.371m	169.864ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.680s	161.095us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.310m	9.783ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.310m	9.783ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.310m	9.783ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.242m	8.394ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	44.110s	958.944us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.310m	9.783ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.123m	17.408ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.242m	8.394ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	4.021m	6.244ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			931	940	99.04

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.65	97.69	94.41	100.00	73.55	96.04	97.74	96.12

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test kmac_stress_all_with_rand_reset has 2 failures.

    • 1.kmac_stress_all_with_rand_reset.38767100404571178443827150145296805588589772238538233161027097790296184241443
      Line 96, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6519585465 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6519585465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.kmac_stress_all_with_rand_reset.26449989977556843368219144065747447396844988167557945134940001520232152495102
      Line 387, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6872670827 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6872670827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 2 failures:

  • Test kmac_sideload_invalid has 2 failures.

    • 7.kmac_sideload_invalid.36997466990042184041307663739651775450166754923917898735403297641080773628522
      Line 80, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/7.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10195051481 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4e839000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
        UVM_INFO @ 10195051481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 23.kmac_sideload_invalid.101152793100886756512623342207410455462283352718391623630136101494705289087315
      Line 81, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/23.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10207020490 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9ab90000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
        UVM_INFO @ 10207020490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:

  • Test kmac_sideload_invalid has 2 failures.

    • 21.kmac_sideload_invalid.71539174761376802041101420040375976341384293572138808114157108631830583511950
      Line 76, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/21.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10020043867 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb7cce000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
        UVM_INFO @ 10020043867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 24.kmac_sideload_invalid.84319281506716134916435666848016076013431905137468522208989374729055051806705
      Line 76, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/24.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10126417742 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x798a7000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
        UVM_INFO @ 10126417742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 2.kmac_sideload_invalid.26387928055345146793707642020723156211182673953172725672483714312659113563187
      Line 82, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/2.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10192829184 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc37d4000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
        UVM_INFO @ 10192829184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 16.kmac_sideload_invalid.7813111913765349564309473508526265337455429375848010033280316297893163095974
      Line 77, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/16.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10200576584 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x92f5c000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
        UVM_INFO @ 10200576584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 36.kmac_sideload_invalid.88931887376288846137513426276019558090437624163683598640104317923192748979562
      Line 75, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/36.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10017125954 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xba7c7000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
        UVM_INFO @ 10017125954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---