OTBN Simulation Results

Sunday October 26 2025 00:06:53 UTC

GitHub Revision: 06d697f

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 12.000s 37.400us 0 1 0.00
V1 single_binary otbn_single 4.267m 970.754us 0 100 0.00
V1 csr_hw_reset otbn_csr_hw_reset 6.000s 26.951us 5 5 100.00
V1 csr_rw otbn_csr_rw 4.000s 50.654us 20 20 100.00
V1 csr_bit_bash otbn_csr_bit_bash 6.000s 195.874us 5 5 100.00
V1 csr_aliasing otbn_csr_aliasing 4.000s 44.314us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 7.000s 258.139us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 4.000s 50.654us 20 20 100.00
otbn_csr_aliasing 4.000s 44.314us 5 5 100.00
V1 mem_walk otbn_mem_walk 43.000s 2.393ms 5 5 100.00
V1 mem_partial_access otbn_mem_partial_access 21.000s 739.428us 5 5 100.00
V1 TOTAL 65 166 39.16
V2 reset_recovery otbn_reset 48.000s 155.226us 0 10 0.00
V2 multi_error otbn_multi_err 1.033m 550.181us 0 1 0.00
V2 back_to_back otbn_multi 1.083m 1.008ms 0 10 0.00
V2 stress_all otbn_stress_all 2.967m 823.525us 0 10 0.00
V2 lc_escalation otbn_escalate 1.150m 286.846us 20 60 33.33
V2 zero_state_err_urnd otbn_zero_state_err_urnd 10.000s 72.226us 4 5 80.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 16.000s 39.413us 0 10 0.00
V2 alert_test otbn_alert_test 9.000s 17.783us 50 50 100.00
V2 intr_test otbn_intr_test 7.000s 25.350us 50 50 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 8.000s 284.819us 20 20 100.00
V2 tl_d_illegal_access otbn_tl_errors 8.000s 284.819us 20 20 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 6.000s 26.951us 5 5 100.00
otbn_csr_rw 4.000s 50.654us 20 20 100.00
otbn_csr_aliasing 4.000s 44.314us 5 5 100.00
otbn_same_csr_outstanding 6.000s 25.232us 20 20 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 6.000s 26.951us 5 5 100.00
otbn_csr_rw 4.000s 50.654us 20 20 100.00
otbn_csr_aliasing 4.000s 44.314us 5 5 100.00
otbn_same_csr_outstanding 6.000s 25.232us 20 20 100.00
V2 TOTAL 164 246 66.67
V2S mem_integrity otbn_imem_err 10.000s 19.989us 1 10 10.00
otbn_dmem_err 19.000s 69.119us 0 15 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 17.000s 116.873us 0 5 0.00
otbn_controller_ispr_rdata_err 11.000s 49.699us 0 5 0.00
otbn_mac_bignum_acc_err 48.000s 256.587us 0 5 0.00
otbn_urnd_err 10.000s 31.624us 0 2 0.00
V2S illegal_bus_access otbn_illegal_mem_acc 9.000s 112.389us 4 5 80.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 8.000s 30.405us 2 2 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 15.963s 9 10 90.00
V2S tl_intg_err otbn_sec_cm 12.317m 3.265ms 5 5 100.00
otbn_tl_intg_err 46.000s 289.074us 20 20 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 32.000s 294.623us 19 20 95.00
V2S prim_fsm_check otbn_sec_cm 12.317m 3.265ms 5 5 100.00
V2S prim_count_check otbn_sec_cm 12.317m 3.265ms 5 5 100.00
V2S sec_cm_mem_scramble otbn_smoke 12.000s 37.400us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 19.000s 69.119us 0 15 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 10.000s 19.989us 1 10 10.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 46.000s 289.074us 20 20 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 1.150m 286.846us 20 60 33.33
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 10.000s 19.989us 1 10 10.00
otbn_dmem_err 19.000s 69.119us 0 15 0.00
otbn_zero_state_err_urnd 10.000s 72.226us 4 5 80.00
otbn_illegal_mem_acc 9.000s 112.389us 4 5 80.00
otbn_sec_cm 12.317m 3.265ms 5 5 100.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 12.317m 3.265ms 5 5 100.00
V2S sec_cm_scramble_key_sideload otbn_single 4.267m 970.754us 0 100 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 10.000s 19.989us 1 10 10.00
otbn_dmem_err 19.000s 69.119us 0 15 0.00
otbn_zero_state_err_urnd 10.000s 72.226us 4 5 80.00
otbn_illegal_mem_acc 9.000s 112.389us 4 5 80.00
otbn_sec_cm 12.317m 3.265ms 5 5 100.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 12.317m 3.265ms 5 5 100.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 1.150m 286.846us 20 60 33.33
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 10.000s 19.989us 1 10 10.00
otbn_dmem_err 19.000s 69.119us 0 15 0.00
otbn_zero_state_err_urnd 10.000s 72.226us 4 5 80.00
otbn_illegal_mem_acc 9.000s 112.389us 4 5 80.00
otbn_sec_cm 12.317m 3.265ms 5 5 100.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 12.317m 3.265ms 5 5 100.00
V2S sec_cm_data_reg_sw_sca otbn_single 4.267m 970.754us 0 100 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 9.000s 29.610us 0 12 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 10.000s 129.183us 4 5 80.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 1.067m 1.078ms 0 5 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 1.067m 1.078ms 0 5 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 11.000s 111.861us 0 10 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 12.317m 3.265ms 5 5 100.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 12.317m 3.265ms 5 5 100.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 11.000s 55.977us 0 10 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 12.317m 3.265ms 5 5 100.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 12.317m 3.265ms 5 5 100.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 10.000s 22.791us 0 5 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 10.000s 22.791us 0 5 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 18.000s 30.783us 4 7 57.14
V2S sec_cm_data_mem_sec_wipe otbn_single 4.267m 970.754us 0 100 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 4.267m 970.754us 0 100 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 4.267m 970.754us 0 100 0.00
V2S sec_cm_write_mem_integrity otbn_multi 1.083m 1.008ms 0 10 0.00
V2S sec_cm_ctrl_flow_count otbn_single 4.267m 970.754us 0 100 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 4.267m 970.754us 0 100 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 47.000s 183.494us 0 5 0.00
V2S sec_cm_key_sideload otbn_single 4.267m 970.754us 0 100 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 12.317m 3.265ms 5 5 100.00
V2S TOTAL 68 163 41.72
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 5.683m 5.536ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 297 585 50.77

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
93.95 97.89 72.63 97.08 78.18 59.24 87.18 80.56 98.29

Failure Buckets