06d697f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 35.000s | 135.962us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 2.000s | 117.655us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 2.000s | 16.555us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 5.000s | 563.255us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 2.000s | 14.870us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 2.000s | 410.902us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 2.000s | 16.555us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 2.000s | 14.870us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 59.000m | 600.000ms | 24 | 50 | 48.00 |
| V2 | cnt_rollover | cnt_rollover | 1.800m | 3.467ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 35.000s | 532.545us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 2.907h | 8.676s | 22 | 50 | 44.00 |
| V2 | alert_test | pattgen_alert_test | 33.000s | 11.659us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 2.000s | 29.082us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 4.000s | 126.114us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 4.000s | 126.114us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 2.000s | 117.655us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 2.000s | 16.555us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 2.000s | 14.870us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 2.000s | 25.010us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 2.000s | 117.655us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 2.000s | 16.555us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 2.000s | 14.870us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 2.000s | 25.010us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 286 | 340 | 84.12 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 3.000s | 78.509us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 34.000s | 148.077us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 3.000s | 78.509us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 2.600m | 6.145ms | 2 | 50 | 4.00 |
| V3 | TOTAL | 2 | 50 | 4.00 | |||
| Unmapped tests | pattgen_inactive_level | 4.450m | 10.014ms | 31 | 50 | 62.00 | |
| TOTAL | 449 | 570 | 78.77 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.53 | 100.00 | 100.00 | 100.00 | 98.50 | 96.61 | -- | 96.95 | 89.42 |
UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 47 failures:
0.pattgen_stress_all_with_rand_reset.100296178514687328466554720011575038705426953789096006355273171100645968680945
Line 224, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5831712929 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 5831743253 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 5831743253 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/10
UVM_INFO @ 5831993255 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
1.pattgen_stress_all_with_rand_reset.109645517730801178977688788047911037694130721598197606608474174884607675647126
Line 148, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2473678299 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 2473688307 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2473688307 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 2473854975 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
... and 45 more failures.
Job timed out after * minutes has 24 failures:
0.pattgen_stress_all.21422248862871308648425834370979270283496686117286657857670081140662053027768
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
1.pattgen_stress_all.9818710728358846590563161836326825132953160776471332688378595882986838372495
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
... and 8 more failures.
1.pattgen_perf.84833657140888477111467958139591901232925046387199703815149843601024862987628
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_perf/latest/run.log
Job timed out after 60 minutes
2.pattgen_perf.37974309203198065460983389189074963559802790858789642992994455792403015877691
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/2.pattgen_perf/latest/run.log
Job timed out after 60 minutes
... and 12 more failures.
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 18 failures:
3.pattgen_stress_all.3300015720984185295734357420730110499654024898475372008129147393008503703056
Line 127, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/3.pattgen_stress_all/latest/run.log
UVM_ERROR @ 262338675 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10177
4.pattgen_stress_all.95122785311720112647078797099299771387235305345858101674184413603528256417939
Line 149, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/4.pattgen_stress_all/latest/run.log
UVM_ERROR @ 65689194870 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
----------------------------------------
Name Type Size Value
----------------------------------------
exp_item pattgen_item - @10996
... and 16 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 12 failures:
10.pattgen_perf.4105447012352006224548793147846599686108324144244407078577789040421264673140
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/10.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.pattgen_perf.54448626101071180095137869533792770466786810951635445176723196876761225867778
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/17.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 3 failures:
2.pattgen_inactive_level.79744666309437178343848090313038540378316547296303386350857478057332433366767
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/2.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10028381608 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x5106890, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10028381608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.pattgen_inactive_level.85848494192759463813796251855521358345915768057006567144795741391597543749134
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/17.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10015940143 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x6c57ca50, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10015940143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
4.pattgen_inactive_level.36996167068117839108010589275566760597195958070251368169974976516034057536989
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/4.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10008520640 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xdda42f50, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10008520640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.pattgen_inactive_level.91066982617859818366546264802037202395319521020473518005839083114456015532140
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/30.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10001379565 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x3d30ba10, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10001379565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 3 failures:
20.pattgen_inactive_level.19251412620356416329797379965250324558759156761086355112880659556241752071355
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/20.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10004199141 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xfd485250, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10004199141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.pattgen_inactive_level.29796349566280608952060840183608520620549272735856519685344093525581959282273
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/25.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10007368790 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x1aca2250, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10007368790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 2 failures:
5.pattgen_inactive_level.5653304490509779777275425305218669425729739697992841268748017622747546941470
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/5.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10017887693 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xc5af2590, Comparison=CompareOpEq, exp_data=0x0, call_count=18)
UVM_INFO @ 10017887693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.pattgen_inactive_level.63789400404214135225157344123462494647483747721194675621221904703657409854974
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/48.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10013997810 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xcbeea6d0, Comparison=CompareOpEq, exp_data=0x0, call_count=18)
UVM_INFO @ 10013997810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 2 failures:
18.pattgen_inactive_level.13911871992747482028523653843124392585352995072363001169735419766794808153599
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/18.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10028712634 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x2f95f910, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10028712634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.pattgen_inactive_level.39655523992554549438811198395688182390102730039303165936088400154304138499494
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/27.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10045457223 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xfe1a6c90, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10045457223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
12.pattgen_inactive_level.2727028544909758727744786351994004027154386118939729829445146624131381807506
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/12.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10663507485 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xf72ea490, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10663507485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=28) has 1 failures:
16.pattgen_inactive_level.100756150023356005878207411190673345064097745149475288516011619401116706784495
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/16.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10124095688 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x75340b90, Comparison=CompareOpEq, exp_data=0x0, call_count=28)
UVM_INFO @ 10124095688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
24.pattgen_inactive_level.40929170349048999696280675183140728865028642540543171865123256097994415339668
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/24.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10631565944 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x8a917790, Comparison=CompareOpEq, exp_data=0x0, call_count=21)
UVM_INFO @ 10631565944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
28.pattgen_inactive_level.86163049875284697521549076710664414898385527798863666979633351165830781191279
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/28.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10051288802 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x9ce9ef10, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
UVM_INFO @ 10051288802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
41.pattgen_inactive_level.13899402935849806320155948608991649533845214886906778578172408009185053088225
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/41.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10049062313 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xcb9ed650, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
UVM_INFO @ 10049062313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=25) has 1 failures:
43.pattgen_inactive_level.75082153859921715503407331048666915610087655542361336057050482711484524233373
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/43.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10155475059 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x6e10b590, Comparison=CompareOpEq, exp_data=0x0, call_count=25)
UVM_INFO @ 10155475059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard] has 1 failures:
47.pattgen_stress_all_with_rand_reset.34296795529449910508983895260739995120628692549403182949335682923517860552969
Line 117, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/47.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 246487091 ps: (pattgen_scoreboard.sv:263) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 1 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value