06d697f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 4.930s | 319.959us | 2 | 2 | 100.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 8.040s | 244.017us | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 6.770s | 2.091ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 5.590s | 288.934us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 7.530s | 535.833us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 8.250s | 186.524us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 6.770s | 2.091ms | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 7.530s | 535.833us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 7.910s | 1.748ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 7.140s | 171.213us | 5 | 5 | 100.00 |
| V1 | TOTAL | 67 | 67 | 100.00 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 5.580s | 186.029us | 2 | 2 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 28.250s | 9.988ms | 20 | 20 | 100.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 6.770s | 377.708us | 2 | 2 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 6.180s | 1.453ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 10.210s | 168.415us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 10.210s | 168.415us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 8.040s | 244.017us | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 6.770s | 2.091ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 7.530s | 535.833us | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 8.100s | 549.215us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 8.040s | 244.017us | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 6.770s | 2.091ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 7.530s | 535.833us | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 8.100s | 549.215us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 114 | 114 | 100.00 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 1.648m | 26.410ms | 15 | 20 | 75.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 32.550s | 11.987ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 4.354m | 984.991us | 1 | 5 | 20.00 |
| rom_ctrl_tl_intg_err | 56.370s | 673.812us | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 4.354m | 984.991us | 1 | 5 | 20.00 |
| V2S | prim_count_check | rom_ctrl_sec_cm | 4.354m | 984.991us | 1 | 5 | 20.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.648m | 26.410ms | 15 | 20 | 75.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.648m | 26.410ms | 15 | 20 | 75.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 1.648m | 26.410ms | 15 | 20 | 75.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.648m | 26.410ms | 15 | 20 | 75.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.648m | 26.410ms | 15 | 20 | 75.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 4.354m | 984.991us | 1 | 5 | 20.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 4.354m | 984.991us | 1 | 5 | 20.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 4.930s | 319.959us | 2 | 2 | 100.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 4.930s | 319.959us | 2 | 2 | 100.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 4.930s | 319.959us | 2 | 2 | 100.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 56.370s | 673.812us | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 1.648m | 26.410ms | 15 | 20 | 75.00 |
| rom_ctrl_kmac_err_chk | 6.770s | 377.708us | 2 | 2 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 1.648m | 26.410ms | 15 | 20 | 75.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.648m | 26.410ms | 15 | 20 | 75.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 1.648m | 26.410ms | 15 | 20 | 75.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 32.550s | 11.987ms | 20 | 20 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 4.354m | 984.991us | 1 | 5 | 20.00 |
| V2S | TOTAL | 56 | 65 | 86.15 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 6.161m | 5.046ms | 20 | 20 | 100.00 |
| V3 | TOTAL | 20 | 20 | 100.00 | |||
| TOTAL | 257 | 266 | 96.62 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.14 | 99.59 | 98.66 | 100.00 | 100.00 | 99.64 | 96.80 | 99.28 |
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 5 failures:
7.rom_ctrl_corrupt_sig_fatal_chk.35268531405666688583391777308586156591063624635970298004845860922393411676174
Line 77, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_ERROR @ 612517827 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 612517827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.rom_ctrl_corrupt_sig_fatal_chk.64640994111944012506883307285817121591143212118551347122250869982371226915683
Line 75, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_ERROR @ 85886986 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 85886986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 2 failures:
0.rom_ctrl_sec_cm.82702227359057329533836591652504409494433836708668786375759676427153380170330
Line 221, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 13465302ps failed at 13465302ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 13465302ps failed at 13465302ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
3.rom_ctrl_sec_cm.63318469826063207063227674699362007397446813192509256137927338439210876599777
Line 302, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_sec_cm/latest/run.log
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 121950511ps failed at 121950511ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 121950511ps failed at 121950511ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 2 failures:
2.rom_ctrl_sec_cm.115196110206879616962534697916202584237093045351740174263312002499306182720330
Line 164, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_sec_cm/latest/run.log
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 28041010ps failed at 28041010ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 38698991ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 38698991ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
4.rom_ctrl_sec_cm.446105873867443178199881261548299459034658358808898655057055443445444865654
Line 232, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_sec_cm/latest/run.log
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 27704394ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 27704394ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
Starting assertion attempts at time 27704394ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))