ROM_CTRL/64KB Simulation Results

Sunday October 26 2025 00:06:53 UTC

GitHub Revision: 06d697f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	8.890s	313.773us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	19.020s	1.046ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	14.780s	2.093ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	10.530s	297.034us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	11.180s	1.025ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	14.110s	7.744ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	14.780s	2.093ms	20	20	100.00
		rom_ctrl_csr_aliasing	11.180s	1.025ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	12.100s	290.434us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	11.940s	303.593us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	10.940s	7.126ms	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	48.720s	1.695ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	17.040s	394.624us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	11.360s	1.066ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	16.660s	295.263us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	16.660s	295.263us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	19.020s	1.046ms	5	5	100.00
		rom_ctrl_csr_rw	14.780s	2.093ms	20	20	100.00
		rom_ctrl_csr_aliasing	11.180s	1.025ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.900s	2.104ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	19.020s	1.046ms	5	5	100.00
		rom_ctrl_csr_rw	14.780s	2.093ms	20	20	100.00
		rom_ctrl_csr_aliasing	11.180s	1.025ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.900s	2.104ms	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.638m	15.566ms	20	20	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	59.940s	1.557ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	9.392m	2.003ms	2	5	40.00
		rom_ctrl_tl_intg_err	2.058m	683.237us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	9.392m	2.003ms	2	5	40.00
V2S	prim_count_check	rom_ctrl_sec_cm	9.392m	2.003ms	2	5	40.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.638m	15.566ms	20	20	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.638m	15.566ms	20	20	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.638m	15.566ms	20	20	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.638m	15.566ms	20	20	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.638m	15.566ms	20	20	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	9.392m	2.003ms	2	5	40.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	9.392m	2.003ms	2	5	40.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	8.890s	313.773us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	8.890s	313.773us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	8.890s	313.773us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.058m	683.237us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.638m	15.566ms	20	20	100.00
		rom_ctrl_kmac_err_chk	17.040s	394.624us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.638m	15.566ms	20	20	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.638m	15.566ms	20	20	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.638m	15.566ms	20	20	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	59.940s	1.557ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	9.392m	2.003ms	2	5	40.00
V2S		TOTAL			62	65	95.38
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	5.053m	6.618ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			263	266	98.87

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.14	99.59	98.66	100.00	100.00	99.64	96.80	99.28

Failure Buckets

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 2 failures:

  • Test rom_ctrl_sec_cm has 2 failures.

    • 1.rom_ctrl_sec_cm.112677471247825887371883671107931117319226525090135856242064992312436887913193
      Line 122, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 29934109ps failed at 29934109ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 29934109ps failed at 29934109ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

    • 2.rom_ctrl_sec_cm.14996772449908242339744041286656555549114278893411306451508254156113961417702
      Line 189, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 51956584ps failed at 51956584ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 51956584ps failed at 51956584ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 4.rom_ctrl_sec_cm.32064874810003803453204718343797394344432431869727528068006944751773278809189
      Line 114, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 8944275ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 8944275ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
        Starting assertion attempts at time 8944275ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))