RV_TIMER Simulation Results

Sunday October 26 2025 00:06:53 UTC

GitHub Revision: `06d697f`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	2.440s	485.016us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.760s	62.415us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.760s	16.989us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.050s	238.654us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.850s	133.918us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.180s	55.255us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.760s	16.989us	20	20	100.00
		rv_timer_csr_aliasing	0.850s	133.918us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	16.770s	69.566ms	2	20	10.00
V2	disabled	rv_timer_disabled	4.510s	2.398ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	9.624m	963.318ms	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	9.624m	963.318ms	10	10	100.00
V2	stress	rv_timer_stress_all	14.480s	8.694ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	0.930s	43.981us	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.880s	39.493us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.200s	157.767us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.200s	157.767us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.760s	62.415us	5	5	100.00
		rv_timer_csr_rw	0.760s	16.989us	20	20	100.00
		rv_timer_csr_aliasing	0.850s	133.918us	5	5	100.00
		rv_timer_same_csr_outstanding	0.850s	14.128us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.760s	62.415us	5	5	100.00
		rv_timer_csr_rw	0.760s	16.989us	20	20	100.00
		rv_timer_csr_aliasing	0.850s	133.918us	5	5	100.00
		rv_timer_same_csr_outstanding	0.850s	14.128us	20	20	100.00
V2		TOTAL			192	210	91.43
V2S	tl_intg_err	rv_timer_sec_cm	1.380s	234.023us	5	5	100.00
		rv_timer_tl_intg_err	1.400s	119.322us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.400s	119.322us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	min_value	rv_timer_min	1.890s	275.301us	1	10	10.00
V3	max_value	rv_timer_max	1.730s	997.999us	0	10	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	43.080s	47.272ms	14	20	70.00
V3		TOTAL			15	40	37.50
		TOTAL			307	350	87.71

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.77	100.00	100.00	78.66	--	100.00	96.82	99.12

Failure Buckets

UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 27 failures:
- Test rv_timer_min has 9 failures.
  - 0.rv_timer_min.52825601598984763065532032805632756595178247002999133695840971929950320366978
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
```
  UVM_FATAL @  69723282 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x9104904) == 0x1
  UVM_INFO @  69723282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_min.91182699064263478117408133536880466727380232380398107025063227400412840343489
    Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_min/latest/run.log
```
  UVM_FATAL @ 219807916 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x71913b04) == 0x1
  UVM_INFO @ 219807916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.
- Test rv_timer_random_reset has 18 failures.
  - 0.rv_timer_random_reset.82063515514937518570500051295596219883261417188014756173291744095106523671835
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 113720317 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xaf05ef04) == 0x1
  UVM_INFO @ 113720317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.rv_timer_random_reset.33206233408072405685924163891644132431360987176818940874250058614751984608761
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/2.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 778875205 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x9ad44d04) == 0x1
  UVM_INFO @ 778875205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 16 more failures.
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 9 failures:
- Test rv_timer_max has 9 failures.
  - 1.rv_timer_max.1520124397160089423600545837344023080661886692215773246129335323688665366682
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_max/latest/run.log
```
  UVM_ERROR @  87088982 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @  87088982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.rv_timer_max.73024142609938247611103140965007096144327457538173149920421106389386123752288
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/2.rv_timer_max/latest/run.log
```
  UVM_ERROR @  88714981 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @  88714981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.
UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 4 failures:
- Test rv_timer_stress_all_with_rand_reset has 4 failures.
  - 9.rv_timer_stress_all_with_rand_reset.62679811961240104573787674358163955559599860445218690117626455453900580975591
    Line 367, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/9.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 47271948264 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
  UVM_INFO @ 47271948264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 13.rv_timer_stress_all_with_rand_reset.24199673201572964206944004073385904772916603515319441306483682199511037250376
    Line 148, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/13.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3101345230 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
  UVM_INFO @ 3101345230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test rv_timer_stress_all_with_rand_reset has 2 failures.

5.rv_timer_stress_all_with_rand_reset.68925506906133414017302098735383767360128021116244226364856267093007229494467
Line 237, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/5.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2308185482 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2308185482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.rv_timer_stress_all_with_rand_reset.75846395699027926141025904749346074408109898289615248531027108922794684031119
Line 202, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/10.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2155506796 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2155506796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rv_timer_scoreboard.sv:365) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) has 1 failures:
- Test rv_timer_max has 1 failures.
  - 0.rv_timer_max.64218335900594361206113058895518866374755241997257963427738290002154361024240
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
```
  UVM_ERROR @ 353132785 ps: (rv_timer_scoreboard.sv:365) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (0x0 [0] vs 0x1 [1])
  UVM_INFO @ 353132785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```