SPI_DEVICE/1R1W Simulation Results

Sunday October 26 2025 00:06:53 UTC

GitHub Revision: `06d697f`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	6.800m	57.721ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.780s	94.991us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.080s	43.237us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	20.100s	7.824ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.420s	601.694us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.850s	122.049us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.080s	43.237us	20	20	100.00
		spi_device_csr_aliasing	15.420s	601.694us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.020s	12.149us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.560s	56.401us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.200s	67.546us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.090s	3.900us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.050s	3.239us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	8.330s	174.784us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.330s	174.784us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	26.920s	8.583ms	50	50	100.00
		spi_device_tpm_sts_read	1.500s	147.218us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	48.040s	31.478ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	52.650s	16.579ms	50	50	100.00
		spi_device_flash_all	5.297m	223.027ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	31.820s	7.537ms	50	50	100.00
		spi_device_flash_all	5.297m	223.027ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	31.820s	7.537ms	50	50	100.00
		spi_device_flash_all	5.297m	223.027ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	5.297m	223.027ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	28.850s	11.410ms	50	50	100.00
		spi_device_flash_all	5.297m	223.027ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	28.850s	11.410ms	50	50	100.00
		spi_device_flash_all	5.297m	223.027ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	28.850s	11.410ms	50	50	100.00
		spi_device_flash_all	5.297m	223.027ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	28.850s	11.410ms	50	50	100.00
		spi_device_flash_all	5.297m	223.027ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	28.850s	11.410ms	50	50	100.00
		spi_device_flash_all	5.297m	223.027ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	42.640s	41.119ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.593m	14.623ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.593m	14.623ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.593m	14.623ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.022m	4.007ms	50	50	100.00
		spi_device_read_buffer_direct	18.160s	6.253ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.593m	14.623ms	50	50	100.00
		spi_device_flash_all	5.297m	223.027ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	5.297m	223.027ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	5.297m	223.027ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	24.970s	6.272ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	24.970s	6.272ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	6.800m	57.721ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.433m	81.832ms	49	50	98.00
V2	stress_all	spi_device_stress_all	9.862m	321.941ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.130s	12.484us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.180s	17.680us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.100s	305.566us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.100s	305.566us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.780s	94.991us	5	5	100.00
		spi_device_csr_rw	3.080s	43.237us	20	20	100.00
		spi_device_csr_aliasing	15.420s	601.694us	5	5	100.00
		spi_device_same_csr_outstanding	4.720s	194.852us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.780s	94.991us	5	5	100.00
		spi_device_csr_rw	3.080s	43.237us	20	20	100.00
		spi_device_csr_aliasing	15.420s	601.694us	5	5	100.00
		spi_device_same_csr_outstanding	4.720s	194.852us	20	20	100.00
V2		TOTAL			939	961	97.71
V2S	tl_intg_err	spi_device_sec_cm	1.750s	91.010us	5	5	100.00
		spi_device_tl_intg_err	20.400s	1.456ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	20.400s	1.456ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.995m	67.809ms	48	50	96.00
		TOTAL			1127	1151	97.91

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.61	99.11	96.57	71.19	89.36	98.40	94.43	99.21

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.96656636780042636073422272673625714772614292359513968735372480347289353159469
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   4701764 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[92])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   4701764 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   4701764 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[988])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.24702820904164350909309068054030541875472993472865094592931707816572427474112
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2538922 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[69])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2538922 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2538922 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[965])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

Test spi_device_ram_cfg has 1 failures.

0.spi_device_ram_cfg.106051604412459950753944696324010234811430915894293700388310146578804322645054
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

  UVM_ERROR @    847414 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x862bc5 [100001100010101111000101] vs 0x0 [0])
  UVM_ERROR @    873414 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa9d131 [101010011101000100110001] vs 0x0 [0])
  UVM_ERROR @    934414 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa09e8e [101000001001111010001110] vs 0x0 [0])
  UVM_ERROR @    944414 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x20e791 [1000001110011110010001] vs 0x0 [0])
  UVM_ERROR @   1007414 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf72bf5 [111101110010101111110101] vs 0x0 [0])

Job timed out after * minutes has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 14.spi_device_flash_mode_ignore_cmds.59315017018171506051736475599936328935288039650825334436166919387966522086364
    Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/14.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  Job timed out after 60 minutes
```

UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == gmv(csr) (* [] vs * []) CSR last_read_addr compare mismatch act * != exp *` has 1 failures:

Test spi_device_flash_mode_ignore_cmds has 1 failures.

37.spi_device_flash_mode_ignore_cmds.110301314391218465297976876088273034588591463729272202884727130082827818278621
Line 99, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/37.spi_device_flash_mode_ignore_cmds/latest/run.log

  UVM_ERROR @ 44208944577 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (8570880 [0x82c800] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0x82c800 != exp 0x0
  UVM_INFO @ 45035535577 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 6/13
  UVM_INFO @ 45035535577 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 7/13
  tl_ul_fuzzy_flash_status_q[i] = 0x72b3a8
  tl_ul_fuzzy_flash_status_q[i] = 0xa020

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_device_flash_and_tpm_min_idle has 1 failures.
  - 42.spi_device_flash_and_tpm_min_idle.15347542433417377334452335478990071678701974147393668431880347525042369464915
    Line 139, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/42.spi_device_flash_and_tpm_min_idle/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```