SPI_DEVICE/2P Simulation Results

Sunday October 26 2025 00:06:53 UTC

GitHub Revision: `06d697f`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	7.593m	81.449ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.630s	147.457us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.950s	92.626us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	31.860s	12.243ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	19.110s	5.357ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.060s	260.896us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.950s	92.626us	20	20	100.00
		spi_device_csr_aliasing	19.110s	5.357ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.070s	41.350us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.220s	27.904us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.210s	17.139us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.480s	24.373us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.930s	17.330us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	8.140s	258.349us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.140s	258.349us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	21.870s	14.296ms	50	50	100.00
		spi_device_tpm_sts_read	1.530s	131.233us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	38.870s	41.346ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	32.730s	10.543ms	50	50	100.00
		spi_device_flash_all	5.377m	110.868ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	32.350s	41.000ms	50	50	100.00
		spi_device_flash_all	5.377m	110.868ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	32.350s	41.000ms	50	50	100.00
		spi_device_flash_all	5.377m	110.868ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	5.377m	110.868ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	21.550s	12.089ms	50	50	100.00
		spi_device_flash_all	5.377m	110.868ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	21.550s	12.089ms	50	50	100.00
		spi_device_flash_all	5.377m	110.868ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	21.550s	12.089ms	50	50	100.00
		spi_device_flash_all	5.377m	110.868ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	21.550s	12.089ms	50	50	100.00
		spi_device_flash_all	5.377m	110.868ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	21.550s	12.089ms	50	50	100.00
		spi_device_flash_all	5.377m	110.868ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	27.650s	11.290ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.243m	18.418ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.243m	18.418ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.243m	18.418ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	37.490s	5.980ms	49	50	98.00
		spi_device_read_buffer_direct	13.070s	3.424ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.243m	18.418ms	50	50	100.00
		spi_device_flash_all	5.377m	110.868ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	5.377m	110.868ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	5.377m	110.868ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	21.120s	4.627ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	21.120s	4.627ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	7.593m	81.449ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	6.168m	122.352ms	50	50	100.00
V2	stress_all	spi_device_stress_all	11.007m	95.529ms	49	50	98.00
V2	alert_test	spi_device_alert_test	1.140s	46.439us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.140s	55.376us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.410s	1.573ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.410s	1.573ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.630s	147.457us	5	5	100.00
		spi_device_csr_rw	2.950s	92.626us	20	20	100.00
		spi_device_csr_aliasing	19.110s	5.357ms	5	5	100.00
		spi_device_same_csr_outstanding	4.000s	61.574us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.630s	147.457us	5	5	100.00
		spi_device_csr_rw	2.950s	92.626us	20	20	100.00
		spi_device_csr_aliasing	19.110s	5.357ms	5	5	100.00
		spi_device_same_csr_outstanding	4.000s	61.574us	20	20	100.00
V2		TOTAL			959	961	99.79
V2S	tl_intg_err	spi_device_sec_cm	1.680s	223.377us	5	5	100.00
		spi_device_tl_intg_err	21.670s	6.967ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.670s	6.967ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	3.800m	175.389ms	49	50	98.00
		TOTAL			1148	1151	99.74

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.16	99.17	96.66	74.78	89.36	98.49	94.41	99.26

Failure Buckets

UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == gmv(csr) (* [] vs * []) CSR last_read_addr compare mismatch act * != exp *` has 2 failures:

Test spi_device_stress_all has 1 failures.

23.spi_device_stress_all.8944164113654176944227253720567875954316322706678360233432816525971356887732
Line 87, in log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/23.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 3153314105 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (10442752 [0x9f5800] vs 1 [0x1]) CSR last_read_addr compare mismatch act 0x9f5800 != exp 0x1
  UVM_INFO @ 4739026805 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 3/9
  UVM_INFO @ 5140425471 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 1/11
  UVM_INFO @ 5140425471 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 2/11
  tl_ul_fuzzy_flash_status_q[i] = 0x99758

Test spi_device_flash_mode_ignore_cmds has 1 failures.

49.spi_device_flash_mode_ignore_cmds.96202766265924332278856280792909463946814615299396760722433810327835500176001
Line 97, in log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/49.spi_device_flash_mode_ignore_cmds/latest/run.log

  UVM_ERROR @ 6004011972 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (12870656 [0xc46400] vs 1 [0x1]) CSR last_read_addr compare mismatch act 0xc46400 != exp 0x1
  tl_ul_fuzzy_flash_status_q[i] = 0xa0f54
  UVM_INFO @ 6581643915 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 6/13
  UVM_INFO @ 6581643915 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 7/13
  UVM_INFO @ 7473123573 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 7/13

UVM_ERROR (spi_device_scoreboard.sv:2815) [scoreboard] Check failed |(intr_trigger_pending & interrupt_mask) == * (* [*] vs * [*]) has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 20.spi_device_flash_mode.105508735025101982882234271271289050358126618816837499114742985645265675765965
    Line 73, in log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/20.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 121645818 ps: (spi_device_scoreboard.sv:2815) [uvm_test_top.env.scoreboard] Check failed |(intr_trigger_pending & interrupt_mask) == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 121645818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```