SPI_HOST Simulation Results

Sunday October 26 2025 00:06:53 UTC

GitHub Revision: `06d697f`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.900m	18.056ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	108.126us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	178.881us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	964.431us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	53.482us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	37.170us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	178.881us	20	20	100.00
		spi_host_csr_aliasing	2.000s	53.482us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	16.253us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	32.966us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	2.000s	23.502us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	46.000s	3.619ms	50	50	100.00
		spi_host_error_cmd	2.000s	58.884us	50	50	100.00
		spi_host_event	9.017m	16.759ms	50	50	100.00
V2	clock_rate	spi_host_speed	10.000s	249.371us	50	50	100.00
V2	speed	spi_host_speed	10.000s	249.371us	50	50	100.00
V2	chip_select_timing	spi_host_speed	10.000s	249.371us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	55.000s	1.396ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	34.195us	50	50	100.00
V2	cpol_cpha	spi_host_speed	10.000s	249.371us	50	50	100.00
V2	full_cycle	spi_host_speed	10.000s	249.371us	50	50	100.00
V2	duplex	spi_host_smoke	1.900m	18.056ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	1.900m	18.056ms	50	50	100.00
V2	stress_all	spi_host_stress_all	1.783m	5.240ms	50	50	100.00
V2	spien	spi_host_spien	4.933m	36.628ms	50	50	100.00
V2	stall	spi_host_status_stall	46.650m	1.000s	48	50	96.00
V2	Idlecsbactive	spi_host_idlecsbactive	35.000s	7.319ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	46.000s	3.619ms	50	50	100.00
V2	alert_test	spi_host_alert_test	2.000s	39.011us	50	50	100.00
V2	intr_test	spi_host_intr_test	2.000s	22.546us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	585.937us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	585.937us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	108.126us	5	5	100.00
		spi_host_csr_rw	2.000s	178.881us	20	20	100.00
		spi_host_csr_aliasing	2.000s	53.482us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	227.923us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	108.126us	5	5	100.00
		spi_host_csr_rw	2.000s	178.881us	20	20	100.00
		spi_host_csr_aliasing	2.000s	53.482us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	227.923us	20	20	100.00
V2		TOTAL			688	690	99.71
V2S	tl_intg_err	spi_host_tl_intg_err	3.000s	99.066us	20	20	100.00
		spi_host_sec_cm	2.000s	260.643us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	3.000s	99.066us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	7.983m	53.894ms	9	10	90.00
		TOTAL			837	840	99.64

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
95.09	96.82	93.35	98.69	94.25	73.07	100.00	95.21	90.42

Failure Buckets

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test spi_host_upper_range_clkdiv has 1 failures.
  - 4.spi_host_upper_range_clkdiv.55187873447444630259897098892824294066619082122991921932293244570236572679411
    Line 159, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_host_status_stall has 1 failures.
  - 31.spi_host_status_stall.51349246131331024089876839144570014192037998568971220089113296818547816470269
    Line 14768, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/31.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed has 1 failures:

Test spi_host_status_stall has 1 failures.

12.spi_host_status_stall.50257616963985566116366752434877177255614037081171888157430059081631255177722
Line 4545, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/12.spi_host_status_stall/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 346597671727 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
  UVM_ERROR @ 346597671727 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x1) != neg_value (0x1) - time=346597672000 ps
  UVM_INFO @ 346597671727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---