SRAM_CTRL/MAIN Simulation Results

Sunday October 26 2025 00:06:53 UTC

GitHub Revision: 06d697f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.860m	1.273ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.120s	187.081us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.060s	34.875us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.640s	478.511us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.130s	30.031us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	6.550s	4.870ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.060s	34.875us	20	20	100.00
		sram_ctrl_csr_aliasing	1.130s	30.031us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.637m	21.776ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.831m	18.277ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	22.302m	30.500ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.382m	11.522ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	40.245m	718.505ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	20.454m	40.818ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.718m	60.035ms	50	50	100.00
V2	executable	sram_ctrl_executable	20.161m	50.926ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.794m	2.067ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.415m	45.427ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.746m	12.743ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.804m	4.114ms	50	50	100.00
		sram_ctrl_throughput_w_readback	1.710m	3.263ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	20.919m	16.864ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.310s	2.103ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.415h	771.330ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.120s	137.443us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.750s	304.758us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.750s	304.758us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.120s	187.081us	5	5	100.00
		sram_ctrl_csr_rw	1.060s	34.875us	20	20	100.00
		sram_ctrl_csr_aliasing	1.130s	30.031us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.290s	256.869us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.120s	187.081us	5	5	100.00
		sram_ctrl_csr_rw	1.060s	34.875us	20	20	100.00
		sram_ctrl_csr_aliasing	1.130s	30.031us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.290s	256.869us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	58.220s	100.806ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.230s	9.572us	0	5	0.00
		sram_ctrl_tl_intg_err	4.730s	3.766ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.230s	9.572us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.730s	3.766ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	20.919m	16.864ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	20.919m	16.864ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.060s	34.875us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	20.161m	50.926ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	20.161m	50.926ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	20.161m	50.926ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.718m	60.035ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	9.970s	7.398ms	42	50	84.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	58.220s	100.806ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	9.170s	2.754ms	35	50	70.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.860m	1.273ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.860m	1.273ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	20.161m	50.926ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.230s	9.572us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.718m	60.035ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.230s	9.572us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.230s	9.572us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.860m	1.273ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.230s	9.572us	0	5	0.00
V2S		TOTAL			117	145	80.69
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.047m	2.704ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1162	1190	97.65

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.64	99.11	92.90	85.46	100.00	98.02	95.83	98.14

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 15 failures:
  • Test sram_ctrl_readback_err has 15 failures.

    • 2.sram_ctrl_readback_err.82426919362860278985996199101667259326890122816056017253634483177987579267056
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 695060518 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4b) != exp (0x4d)
        UVM_INFO @ 695060518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 7.sram_ctrl_readback_err.91307824280946145654634013109600765627961221114698985577103910212620052941391
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/7.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 2753756901 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x61) != exp (0x1)
        UVM_INFO @ 2753756901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 13 more failures.

• Offending 'reqfifo_rvalid' has 8 failures:
  • Test sram_ctrl_mubi_enc_err has 8 failures.

    • 3.sram_ctrl_mubi_enc_err.108508125041158898210517136415524607876708486111556774060008532350125244998286
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 2538872659 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 2538872659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 18.sram_ctrl_mubi_enc_err.38104733083570999229820183732892823089436227046326879185291258937647172963610
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/18.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 2440422110 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 2440422110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 6 more failures.

• Offending '(!$isunknown(rdata_o))' has 3 failures:
  • Test sram_ctrl_sec_cm has 3 failures.

    • 0.sram_ctrl_sec_cm.21258398294632617256710730293119379757744037563228503342236385750938625202708
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   2263299 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   2263299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_sec_cm.9998518324566184996906379558716875008334778469850154644737790101601024299307
      Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   9572028 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   9572028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending '(depth_o <= *'(Depth))' has 2 failures:
  • Test sram_ctrl_sec_cm has 2 failures.

    • 1.sram_ctrl_sec_cm.56682480725641253553104646921021824129661586381285203751784476255922904973454
      Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   3949893 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   3949893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.sram_ctrl_sec_cm.56218488495342331767603336226703836732546130140147355585791143347394604061919
      Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @  26112121 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @  26112121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---