SRAM_CTRL/RET Simulation Results

Sunday October 26 2025 00:06:53 UTC

GitHub Revision: 06d697f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.740m	1.321ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.080s	14.713us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.110s	14.484us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.100s	390.514us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.060s	30.363us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.850s	84.735us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.110s	14.484us	20	20	100.00
		sram_ctrl_csr_aliasing	1.060s	30.363us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	15.920s	2.722ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	8.050s	1.490ms	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	29.387m	26.998ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.913m	3.293ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.849m	6.538ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	18.747m	16.703ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	17.170s	7.158ms	50	50	100.00
V2	executable	sram_ctrl_executable	29.342m	97.962ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.465m	691.751us	50	50	100.00
		sram_ctrl_partial_access_b2b	8.968m	22.915ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.688m	146.222us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.493m	153.755us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.722m	1.163ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	22.195m	8.206ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.490s	165.732us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.254h	132.780ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.120s	112.130us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.170s	135.977us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.170s	135.977us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.080s	14.713us	5	5	100.00
		sram_ctrl_csr_rw	1.110s	14.484us	20	20	100.00
		sram_ctrl_csr_aliasing	1.060s	30.363us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.120s	77.230us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.080s	14.713us	5	5	100.00
		sram_ctrl_csr_rw	1.110s	14.484us	20	20	100.00
		sram_ctrl_csr_aliasing	1.060s	30.363us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.120s	77.230us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.450s	760.564us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.200s	8.469us	0	5	0.00
		sram_ctrl_tl_intg_err	4.290s	2.341ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.200s	8.469us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.290s	2.341ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	22.195m	8.206ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	22.195m	8.206ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.110s	14.484us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	29.342m	97.962ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	29.342m	97.962ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	29.342m	97.962ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	17.170s	7.158ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.730s	73.701us	41	50	82.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.450s	760.564us	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.660s	252.509us	34	50	68.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.740m	1.321ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.740m	1.321ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	29.342m	97.962ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.200s	8.469us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	17.170s	7.158ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.200s	8.469us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.200s	8.469us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.740m	1.321ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.200s	8.469us	0	5	0.00
V2S		TOTAL			115	145	79.31
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	11.055m	5.161ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1158	1190	97.31

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.64	99.07	92.90	85.37	100.00	97.98	95.79	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 16 failures:

  • Test sram_ctrl_readback_err has 16 failures.

    • 0.sram_ctrl_readback_err.94079091049440308694292353617372204332040663618469915666532113537537139117395
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  24735516 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4e) != exp (0xd)
        UVM_INFO @  24735516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_readback_err.45134755201417106449283032739765096737810309820101891466540051281699786902160
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  43580577 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3f) != exp (0x0)
        UVM_INFO @  43580577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 14 more failures.

• Offending 'reqfifo_rvalid' has 9 failures:

  • Test sram_ctrl_mubi_enc_err has 9 failures.

    • 7.sram_ctrl_mubi_enc_err.80619833024327977601946402899558495858392280328808428603603689122178469721134
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/7.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  88611581 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  88611581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 11.sram_ctrl_mubi_enc_err.109312005522902657194505028866455333894870292340947096850088145854314509967430
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/11.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  93793412 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  93793412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 7 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 4 failures:

  • Test sram_ctrl_sec_cm has 4 failures.

    • 0.sram_ctrl_sec_cm.43738098708582587348806132613691456574170075432755886507508335183884056049529
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3769316 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3769316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.sram_ctrl_sec_cm.64736628192967120254970701679300262779010075898436117328039117236025263729980
      Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   8468907 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   8468907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 3.sram_ctrl_sec_cm.32582600052765101961448304820550068128140758609132560408849061120164748912639
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @    901297 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @    901297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 13.sram_ctrl_csr_mem_rw_with_rand_reset.85417862484057818494792221455346845741980639419818180319478218526206751361104
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  48282259 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: 0x0
        UVM_INFO @  48282259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 1 failures.

    • 32.sram_ctrl_stress_all_with_rand_reset.22882830053875771155503070044801340309006243374729586295119876964878320384677
      Line 107, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 898054729 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 898054729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---