06d697f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sysrst_ctrl_smoke | 8.370s | 2.108ms | 50 | 50 | 100.00 |
| V1 | input_output_inverted | sysrst_ctrl_in_out_inverted | 10.900s | 2.470ms | 50 | 50 | 100.00 |
| V1 | combo_detect_ec_rst | sysrst_ctrl_combo_detect_ec_rst | 5.090s | 2.205ms | 5 | 5 | 100.00 |
| V1 | combo_detect_ec_rst_with_pre_cond | sysrst_ctrl_combo_detect_ec_rst_with_pre_cond | 5.530s | 2.305ms | 4 | 5 | 80.00 |
| V1 | csr_hw_reset | sysrst_ctrl_csr_hw_reset | 12.400s | 6.043ms | 5 | 5 | 100.00 |
| V1 | csr_rw | sysrst_ctrl_csr_rw | 8.310s | 2.035ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | sysrst_ctrl_csr_bit_bash | 1.256m | 39.108ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sysrst_ctrl_csr_aliasing | 11.950s | 2.507ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sysrst_ctrl_csr_mem_rw_with_rand_reset | 8.850s | 2.044ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sysrst_ctrl_csr_rw | 8.310s | 2.035ms | 20 | 20 | 100.00 |
| sysrst_ctrl_csr_aliasing | 11.950s | 2.507ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 164 | 165 | 99.39 | |||
| V2 | combo_detect | sysrst_ctrl_combo_detect | 7.713m | 204.949ms | 50 | 50 | 100.00 |
| V2 | combo_detect_with_pre_cond | sysrst_ctrl_combo_detect_with_pre_cond | 7.640m | 185.945ms | 88 | 100 | 88.00 |
| V2 | auto_block_key_outputs | sysrst_ctrl_auto_blk_key_output | 7.964m | 165.434ms | 50 | 50 | 100.00 |
| V2 | keyboard_input_triggered_interrupt | sysrst_ctrl_edge_detect | 20.426m | 972.141ms | 49 | 50 | 98.00 |
| V2 | pin_output_keyboard_inversion_control | sysrst_ctrl_pin_override_test | 8.820s | 2.511ms | 50 | 50 | 100.00 |
| V2 | pin_input_value_accessibility | sysrst_ctrl_pin_access_test | 9.080s | 2.225ms | 50 | 50 | 100.00 |
| V2 | ec_power_on_reset | sysrst_ctrl_ec_pwr_on_rst | 40.048m | 983.439ms | 50 | 50 | 100.00 |
| V2 | flash_write_protect_output | sysrst_ctrl_flash_wr_prot_out | 9.410s | 2.615ms | 50 | 50 | 100.00 |
| V2 | ultra_low_power_test | sysrst_ctrl_ultra_low_pwr | 3.991m | 732.768ms | 41 | 50 | 82.00 |
| V2 | sysrst_ctrl_feature_disable | sysrst_ctrl_feature_disable | 22.380s | 40.208ms | 2 | 2 | 100.00 |
| V2 | stress_all | sysrst_ctrl_stress_all | 8.401m | 208.014ms | 48 | 50 | 96.00 |
| V2 | alert_test | sysrst_ctrl_alert_test | 8.070s | 2.015ms | 50 | 50 | 100.00 |
| V2 | intr_test | sysrst_ctrl_intr_test | 8.470s | 2.011ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | sysrst_ctrl_tl_errors | 10.200s | 2.050ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sysrst_ctrl_tl_errors | 10.200s | 2.050ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sysrst_ctrl_csr_hw_reset | 12.400s | 6.043ms | 5 | 5 | 100.00 |
| sysrst_ctrl_csr_rw | 8.310s | 2.035ms | 20 | 20 | 100.00 | ||
| sysrst_ctrl_csr_aliasing | 11.950s | 2.507ms | 5 | 5 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 29.520s | 9.608ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | sysrst_ctrl_csr_hw_reset | 12.400s | 6.043ms | 5 | 5 | 100.00 |
| sysrst_ctrl_csr_rw | 8.310s | 2.035ms | 20 | 20 | 100.00 | ||
| sysrst_ctrl_csr_aliasing | 11.950s | 2.507ms | 5 | 5 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 29.520s | 9.608ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 668 | 692 | 96.53 | |||
| V2S | tl_intg_err | sysrst_ctrl_sec_cm | 1.472m | 42.012ms | 5 | 5 | 100.00 |
| sysrst_ctrl_tl_intg_err | 1.732m | 42.485ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sysrst_ctrl_tl_intg_err | 1.732m | 42.485ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | sysrst_ctrl_stress_all_with_rand_reset | 49.140s | 666.876ms | 47 | 50 | 94.00 |
| V3 | TOTAL | 47 | 50 | 94.00 | |||
| TOTAL | 904 | 932 | 97.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.86 | 99.18 | 98.24 | 100.00 | 98.08 | 99.30 | 98.28 | 91.92 |
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 9 failures:
Test sysrst_ctrl_edge_detect has 1 failures.
0.sysrst_ctrl_edge_detect.111271234386045234877900649983586563219827344802789046077199333636223745010060
Line 388, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_edge_detect/latest/run.log
UVM_ERROR @ 2794889772 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 2794929771 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 2794929771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sysrst_ctrl_stress_all has 1 failures.
6.sysrst_ctrl_stress_all.46763792370462977598775581035980743779893118390154160851648635471654349197603
Line 383, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_stress_all/latest/run.log
UVM_ERROR @ 5090295738 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 5090315737 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 5090315737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sysrst_ctrl_ultra_low_pwr has 6 failures.
13.sysrst_ctrl_ultra_low_pwr.109365061378812912247357090797014237813423205276680380742998733478967059985665
Line 382, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 6776299446 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 6776432779 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 6776432779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.sysrst_ctrl_ultra_low_pwr.47523922333357244530017854194128868164484418022677764346130289404118378609027
Line 382, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 8495151731 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 8495401730 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 8495401730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.
20.sysrst_ctrl_stress_all_with_rand_reset.74322886447954956764128420375843326367864399057971929990459943274727972969519
Line 425, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 15249525481 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 15249747702 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 15249747702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 5 failures:
Test sysrst_ctrl_ultra_low_pwr has 3 failures.
4.sysrst_ctrl_ultra_low_pwr.98835244433875607506245105344907650145193672956495416996838808748598077144073
Line 381, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 4083752539 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_ERROR @ 5216252539 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 5216252539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.sysrst_ctrl_ultra_low_pwr.10168658774266605447997648587409860315102209542227327678039089465411504641865
Line 381, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 2752289209 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 3019789209 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
UVM_ERROR @ 3225138947 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 3225138947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test sysrst_ctrl_stress_all has 1 failures.
8.sysrst_ctrl_stress_all.97671339683327345567643156686768470492420888757051560480234001562886014166739
Line 392, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_stress_all/latest/run.log
UVM_ERROR @ 9761966838 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_ERROR @ 9904466838 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 9904466838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.
12.sysrst_ctrl_stress_all_with_rand_reset.68770856044508827031440141006164266625977463525856497729384822531757949077313
Line 435, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 27509737015 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_ERROR @ 28512237015 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 28512237015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 4 failures:
10.sysrst_ctrl_combo_detect_with_pre_cond.4367064984849125664999858736370197065359109004747954159494493141758732489291
Line 393, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 13754365675 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 13754365675 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 13754365675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.sysrst_ctrl_combo_detect_with_pre_cond.83269669248577760992171231663869067813870329396682433175997407542000314088985
Line 394, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 26033827849 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 36351233171 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x32
UVM_INFO @ 36351317379 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x2c
UVM_INFO @ 36733827849 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0
UVM_INFO @ 36748827849 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= 1d
... and 2 more failures.
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:111) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_l2h_expected == *) Unexpected L2H transition of ec_rst_l_o has 1 failures:
2.sysrst_ctrl_combo_detect_with_pre_cond.113903187848363789252137220751395071820603447127243635967909362596365849779411
Line 396, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 13138343568 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:111) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_l2h_expected == 1) Unexpected L2H transition of ec_rst_l_o
UVM_ERROR @ 13163343568 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_h2l_expected == 1) Unexpected H2L transition of ec_rst_l_o
UVM_INFO @ 13163343568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: * has 1 failures:
4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.101133615659336504839009363801312521517596043766536205772734028082788227963552
Line 383, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest/run.log
UVM_ERROR @ 2292164021 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: 0x0
UVM_INFO @ 2515832437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) has 1 failures:
4.sysrst_ctrl_combo_detect_with_pre_cond.16695888576781459740615650715143377626320207109067702459756787336294282726502
Line 440, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 82910118856 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 82910118856 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 82910118856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(3) +/-* has 1 failures:
5.sysrst_ctrl_combo_detect_with_pre_cond.46588516466648189170927375129905117110511848368477726903506525716880713524960
Line 396, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 15264889889 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(3) +/-4
UVM_INFO @ 15274889889 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:152) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_h2l_expected == 0
UVM_INFO @ 15499889889 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 15519889889 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 25544590617 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x31
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(6) vs exp(2) +/-* has 1 failures:
21.sysrst_ctrl_combo_detect_with_pre_cond.110770409843967458608625648595205343676948958241192227061239451142359090302652
Line 405, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 37984693066 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(6) vs exp(2) +/-4
UVM_ERROR @ 37984693066 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(6) vs exp(2) +/-4
UVM_INFO @ 37984693066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_pin_access_vseq.sv:35) [sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.pwrb_in == rdata_pwrb_in (* [*] vs * [*]) has 1 failures:
37.sysrst_ctrl_stress_all_with_rand_reset.77514622843883628738800825940529292914485537391992242195098027837012744267393
Line 427, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 21938427012 ps: (sysrst_ctrl_pin_access_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.pwrb_in == rdata_pwrb_in (1 [0x1] vs 0 [0x0])
UVM_ERROR @ 21938427012 ps: (sysrst_ctrl_pin_access_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key2_in == rdata_key2_in (1 [0x1] vs 0 [0x0])
UVM_INFO @ 21938427012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(8) vs exp(3) +/-* has 1 failures:
51.sysrst_ctrl_combo_detect_with_pre_cond.45632930284803959012494413148475014424571815926000082519991805443414466768254
Line 404, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/51.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 35370388799 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(8) vs exp(3) +/-4
UVM_INFO @ 35375388799 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:152) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_h2l_expected == 0
UVM_INFO @ 35555388799 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 35575388799 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 45603860893 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x28
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(6) vs exp(2) +/-* has 1 failures:
63.sysrst_ctrl_combo_detect_with_pre_cond.80052849041628105385898779517546392550894140524690904871598076114112280018748
Line 438, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/63.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 60867837855 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(6) vs exp(2) +/-4
UVM_INFO @ 62772837855 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0
UVM_INFO @ 62772837855 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 1
UVM_INFO @ 62772837855 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2
UVM_INFO @ 62787837855 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= a
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(9) vs exp(5) +/-* has 1 failures:
81.sysrst_ctrl_combo_detect_with_pre_cond.102027029208328595356562954685807474636217274097744208300405249923174418031822
Line 412, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/81.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 38636597305 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(9) vs exp(5) +/-4
UVM_ERROR @ 38636597305 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(9) vs exp(5) +/-4
UVM_INFO @ 38636597305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(2) +/-* has 1 failures:
98.sysrst_ctrl_combo_detect_with_pre_cond.88570774146735615385147671184757348057574906676625964821387853241574799136324
Line 405, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/98.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 16823131391 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(2) +/-4
UVM_INFO @ 16828131391 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:152) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_h2l_expected == 0
UVM_INFO @ 16978131391 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 16998131391 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 17579035584 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 1