ADC_CTRL Simulation Results

Sunday November 02 2025 00:09:31 UTC

GitHub Revision: `0136fdb`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	21.050s	6.027ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	4.930s	1.249ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.970s	551.262us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.295m	27.188ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	6.320s	1.267ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.990s	558.339us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.970s	551.262us	20	20	100.00
		adc_ctrl_csr_aliasing	6.320s	1.267ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.084m	492.795ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.053m	490.796ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.028m	485.706ms	49	50	98.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.113m	498.182ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	24.692m	584.614ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.714m	617.965ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	22.629m	600.000ms	47	50	94.00
V2	clock_gating	adc_ctrl_clock_gating	18.382m	498.055ms	35	50	70.00
V2	poweron_counter	adc_ctrl_poweron_counter	18.340s	5.331ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	2.295m	46.421ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	7.012m	134.985ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	24.480m	713.149ms	46	50	92.00
V2	alert_test	adc_ctrl_alert_test	2.640s	530.563us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	2.510s	520.937us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.490s	550.452us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.490s	550.452us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	4.930s	1.249ms	5	5	100.00
		adc_ctrl_csr_rw	2.970s	551.262us	20	20	100.00
		adc_ctrl_csr_aliasing	6.320s	1.267ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.590s	4.738ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	4.930s	1.249ms	5	5	100.00
		adc_ctrl_csr_rw	2.970s	551.262us	20	20	100.00
		adc_ctrl_csr_aliasing	6.320s	1.267ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.590s	4.738ms	20	20	100.00
V2		TOTAL			717	740	96.89
V2S	tl_intg_err	adc_ctrl_sec_cm	20.910s	7.466ms	5	5	100.00
		adc_ctrl_tl_intg_err	21.000s	9.139ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	21.000s	9.139ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	16.634m	10.000s	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			894	920	97.17

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 13 failures:
- Test adc_ctrl_clock_gating has 9 failures.
  - 6.adc_ctrl_clock_gating.6142261779412373774946552771981930680146654232271363779056417576180539440237
    Line 165, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/6.adc_ctrl_clock_gating/latest/run.log
```
  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 12.adc_ctrl_clock_gating.112685084147467371061632505196373030860515090595654786088052997984836464411205
    Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/12.adc_ctrl_clock_gating/latest/run.log
```
  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 30.adc_ctrl_stress_all_with_rand_reset.98472864367223533119112019826573554015995613574712190222457014342049847098903
    Line 197, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test adc_ctrl_filters_both has 2 failures.
  - 31.adc_ctrl_filters_both.108156231832493000872325486116391133287776166465857053010126747969071012947926
    Line 180, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/31.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 38.adc_ctrl_filters_both.91441775580938342358785474742197010836698064774383139700382587752569155382712
    Line 180, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/38.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test adc_ctrl_stress_all has 1 failures.
  - 48.adc_ctrl_stress_all.85464681735398260717527671188715359132489717606915515920188200248579041453957
    Line 149, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/48.adc_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 8 failures:

Test adc_ctrl_clock_gating has 5 failures.

0.adc_ctrl_clock_gating.46816054027296984168272623826896879216800569998995670088483304597144136750355
Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 4329474413 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 4329474413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.adc_ctrl_clock_gating.36118102317869174594299141429727549933942933088609917260149058558047704679810
Line 165, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/2.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 170223995913 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 170223995913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test adc_ctrl_stress_all_with_rand_reset has 2 failures.

4.adc_ctrl_stress_all_with_rand_reset.86230927385362479293848949996496468953799352775407369057598394978778970757566
Line 202, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 56113358389 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 56113358389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.adc_ctrl_stress_all_with_rand_reset.32304833901570024960575116105296980147366883469602610501121582816788435736661
Line 224, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/44.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 63760542776 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 63760542776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_stress_all has 1 failures.

35.adc_ctrl_stress_all.12922151231746022904377366676271971261583168060300943980963828794935560966736
Line 390, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 207806860652 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 207806860652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 5 failures:

Test adc_ctrl_stress_all has 2 failures.

9.adc_ctrl_stress_all.105961409213963727769691939265414271611898002571783414442883156844888603171068
Line 161, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 88193657088 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 88193657088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.adc_ctrl_stress_all.24093979788143395066021005432568531947332777945898790833184574283327610711104
Line 213, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 599568772368 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 599568772368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_clock_gating has 1 failures.

17.adc_ctrl_clock_gating.34247215856811406824906468366513840603204239865804965218330653423988881250757
Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/17.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 82672743130 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 82672743130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_filters_interrupt has 1 failures.

18.adc_ctrl_filters_interrupt.80078304606249269819056486124701053002926821409436258872614641210177678448002
Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/18.adc_ctrl_filters_interrupt/latest/run.log

  UVM_ERROR @ 85162855854 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 85162855854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_filters_both has 1 failures.

32.adc_ctrl_filters_both.62317493820940944361684030005421571090557743690395622395893512032684240325271
Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/32.adc_ctrl_filters_both/latest/run.log

  UVM_ERROR @ 167797673764 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 167797673764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---