AES/MASKED Simulation Results

Sunday November 02 2025 00:09:31 UTC

GitHub Revision: 0136fdb

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	187.937us	1	1	100.00
V1	smoke	aes_smoke	13.000s	414.296us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	124.515us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	80.554us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	2.168ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	203.202us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	73.331us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	80.554us	20	20	100.00
		aes_csr_aliasing	4.000s	203.202us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	13.000s	414.296us	50	50	100.00
		aes_config_error	18.000s	621.490us	50	50	100.00
		aes_stress	47.000s	2.377ms	50	50	100.00
V2	key_length	aes_smoke	13.000s	414.296us	50	50	100.00
		aes_config_error	18.000s	621.490us	50	50	100.00
		aes_stress	47.000s	2.377ms	50	50	100.00
V2	back2back	aes_stress	47.000s	2.377ms	50	50	100.00
		aes_b2b	33.000s	447.939us	50	50	100.00
V2	backpressure	aes_stress	47.000s	2.377ms	50	50	100.00
V2	multi_message	aes_smoke	13.000s	414.296us	50	50	100.00
		aes_config_error	18.000s	621.490us	50	50	100.00
		aes_stress	47.000s	2.377ms	50	50	100.00
		aes_alert_reset	50.000s	2.821ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	190.432us	50	50	100.00
		aes_config_error	18.000s	621.490us	50	50	100.00
		aes_alert_reset	50.000s	2.821ms	50	50	100.00
V2	trigger_clear_test	aes_clear	2.167m	5.055ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	514.973us	1	1	100.00
V2	reset_recovery	aes_alert_reset	50.000s	2.821ms	50	50	100.00
V2	stress	aes_stress	47.000s	2.377ms	50	50	100.00
V2	sideload	aes_stress	47.000s	2.377ms	50	50	100.00
		aes_sideload	28.000s	1.850ms	50	50	100.00
V2	deinitialization	aes_deinit	6.000s	235.873us	50	50	100.00
V2	stress_all	aes_stress_all	1.117m	1.076ms	10	10	100.00
V2	alert_test	aes_alert_test	3.000s	62.296us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	4.000s	645.597us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	4.000s	645.597us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	124.515us	5	5	100.00
		aes_csr_rw	3.000s	80.554us	20	20	100.00
		aes_csr_aliasing	4.000s	203.202us	5	5	100.00
		aes_same_csr_outstanding	4.000s	934.036us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	124.515us	5	5	100.00
		aes_csr_rw	3.000s	80.554us	20	20	100.00
		aes_csr_aliasing	4.000s	203.202us	5	5	100.00
		aes_same_csr_outstanding	4.000s	934.036us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	45.000s	3.469ms	50	50	100.00
V2S	fault_inject	aes_fi	42.000s	1.947ms	50	50	100.00
		aes_control_fi	56.000s	10.006ms	277	300	92.33
		aes_cipher_fi	57.000s	10.127ms	336	350	96.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	66.357us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	66.357us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	66.357us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	66.357us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	436.981us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	986.387us	5	5	100.00
		aes_tl_intg_err	4.000s	429.358us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	4.000s	429.358us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	50.000s	2.821ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	66.357us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	13.000s	414.296us	50	50	100.00
		aes_stress	47.000s	2.377ms	50	50	100.00
		aes_alert_reset	50.000s	2.821ms	50	50	100.00
		aes_core_fi	1.117m	10.008ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	66.357us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	3.000s	62.821us	50	50	100.00
		aes_stress	47.000s	2.377ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	47.000s	2.377ms	50	50	100.00
		aes_sideload	28.000s	1.850ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	3.000s	62.821us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	3.000s	62.821us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	3.000s	62.821us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	3.000s	62.821us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	3.000s	62.821us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	47.000s	2.377ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	47.000s	2.377ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	42.000s	1.947ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	42.000s	1.947ms	50	50	100.00
		aes_control_fi	56.000s	10.006ms	277	300	92.33
		aes_cipher_fi	57.000s	10.127ms	336	350	96.00
		aes_ctr_fi	3.000s	65.233us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	42.000s	1.947ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	42.000s	1.947ms	50	50	100.00
		aes_control_fi	56.000s	10.006ms	277	300	92.33
		aes_cipher_fi	57.000s	10.127ms	336	350	96.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	57.000s	10.127ms	336	350	96.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	42.000s	1.947ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	42.000s	1.947ms	50	50	100.00
		aes_control_fi	56.000s	10.006ms	277	300	92.33
		aes_ctr_fi	3.000s	65.233us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	42.000s	1.947ms	50	50	100.00
		aes_control_fi	56.000s	10.006ms	277	300	92.33
		aes_cipher_fi	57.000s	10.127ms	336	350	96.00
		aes_ctr_fi	3.000s	65.233us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	50.000s	2.821ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	42.000s	1.947ms	50	50	100.00
		aes_control_fi	56.000s	10.006ms	277	300	92.33
		aes_cipher_fi	57.000s	10.127ms	336	350	96.00
		aes_ctr_fi	3.000s	65.233us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	42.000s	1.947ms	50	50	100.00
		aes_control_fi	56.000s	10.006ms	277	300	92.33
		aes_cipher_fi	57.000s	10.127ms	336	350	96.00
		aes_ctr_fi	3.000s	65.233us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	42.000s	1.947ms	50	50	100.00
		aes_control_fi	56.000s	10.006ms	277	300	92.33
		aes_ctr_fi	3.000s	65.233us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	42.000s	1.947ms	50	50	100.00
		aes_control_fi	56.000s	10.006ms	277	300	92.33
		aes_cipher_fi	57.000s	10.127ms	336	350	96.00
V2S		TOTAL			945	985	95.94
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	42.000s	2.572ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1552	1602	96.88

Failure Buckets

• UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 13 failures:

  • Test aes_cipher_fi has 13 failures.

    • 6.aes_cipher_fi.93717528908151199069806869497406841153461698994108119980201564717860076959293
      Line 135, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/6.aes_cipher_fi/latest/run.log

        UVM_FATAL @ 10021808289 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
        UVM_INFO @ 10021808289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 11.aes_cipher_fi.91049884712682730190763528390565390306736616030097059429295390106613758528204
      Line 148, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/11.aes_cipher_fi/latest/run.log

        UVM_FATAL @ 10009268948 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
        UVM_INFO @ 10009268948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 11 more failures.

• Job timed out after * minutes has 13 failures:

  • Test aes_control_fi has 12 failures.

    • 38.aes_control_fi.29548807288508812484988114210060078689377000810869521165086472690666634370135
      Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/38.aes_control_fi/latest/run.log

        Job timed out after 1 minutes
      

    • 63.aes_control_fi.101296049838821474481771150313773160265660203574620093276971146751891232802344
      Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/63.aes_control_fi/latest/run.log

        Job timed out after 1 minutes
      

    • ... and 10 more failures.

  • Test aes_cipher_fi has 1 failures.

    • 164.aes_cipher_fi.78565139071421713887001282241704036704468487165678642985980205692270213278132
      Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/164.aes_cipher_fi/latest/run.log

        Job timed out after 1 minutes
      

• UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 11 failures:

  • Test aes_control_fi has 11 failures.

    • 5.aes_control_fi.42624725995351750739658879747828834319068999511269843274069449968836902185221
      Line 133, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/5.aes_control_fi/latest/run.log

        UVM_FATAL @ 10015472966 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
        UVM_INFO @ 10015472966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 33.aes_control_fi.85845549663896099545003662571137079662141695926858851554692008193195172887428
      Line 140, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/33.aes_control_fi/latest/run.log

        UVM_FATAL @ 10003516763 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
        UVM_INFO @ 10003516763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 9 more failures.

• UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

  • Test aes_stress_all_with_rand_reset has 6 failures.

    • 3.aes_stress_all_with_rand_reset.18459069356027059519315451396288551015168203874922535567554118059619524008346
      Line 965, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1741940108 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
        UVM_INFO @ 1741940108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.aes_stress_all_with_rand_reset.14574458900766843061929672257312494980903270640009583272565493871144500226636
      Line 760, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 505179664 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
        UVM_INFO @ 505179664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 4 more failures.

• UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 3 failures:

  • Test aes_stress_all_with_rand_reset has 3 failures.

    • 0.aes_stress_all_with_rand_reset.94811012107104655237599835736392747667563511145469486270733806134800236299448
      Line 139, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @  94225308 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
        UVM_INFO @  94225308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.aes_stress_all_with_rand_reset.103476264142231707263347469068963659619428593408966152690400424062439819240371
      Line 138, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 257830572 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
        UVM_INFO @ 257830572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:

  • Test aes_core_fi has 3 failures.

    • 1.aes_core_fi.61287013122618175247858244114484594399488682493837658896341655017273861114448
      Line 138, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_core_fi/latest/run.log

        UVM_FATAL @ 10008249709 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
        UVM_INFO @ 10008249709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 13.aes_core_fi.99153512555015110062759007120478905067063475912468110395124993951778115787725
      Line 144, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/13.aes_core_fi/latest/run.log

        UVM_FATAL @ 10014034562 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
        UVM_INFO @ 10014034562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 1.aes_stress_all_with_rand_reset.53808320725526031971783424898364788516781952057444953418128546728180233282122
      Line 321, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1041738935 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1041738935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---