AES/UNMASKED Simulation Results

Sunday November 02 2025 00:09:31 UTC

GitHub Revision: `0136fdb`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	57.885us	1	1	100.00
V1	smoke	aes_smoke	5.000s	201.385us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	15.000s	77.365us	5	5	100.00
V1	csr_rw	aes_csr_rw	11.000s	113.781us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	17.000s	629.970us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	1.465ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	63.842us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	11.000s	113.781us	20	20	100.00
		aes_csr_aliasing	5.000s	1.465ms	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	5.000s	201.385us	50	50	100.00
		aes_config_error	4.000s	136.704us	50	50	100.00
		aes_stress	4.000s	105.061us	50	50	100.00
V2	key_length	aes_smoke	5.000s	201.385us	50	50	100.00
		aes_config_error	4.000s	136.704us	50	50	100.00
		aes_stress	4.000s	105.061us	50	50	100.00
V2	back2back	aes_stress	4.000s	105.061us	50	50	100.00
		aes_b2b	8.000s	514.372us	50	50	100.00
V2	backpressure	aes_stress	4.000s	105.061us	50	50	100.00
V2	multi_message	aes_smoke	5.000s	201.385us	50	50	100.00
		aes_config_error	4.000s	136.704us	50	50	100.00
		aes_stress	4.000s	105.061us	50	50	100.00
		aes_alert_reset	3.000s	211.014us	50	50	100.00
V2	failure_test	aes_man_cfg_err	3.000s	92.313us	50	50	100.00
		aes_config_error	4.000s	136.704us	50	50	100.00
		aes_alert_reset	3.000s	211.014us	50	50	100.00
V2	trigger_clear_test	aes_clear	4.000s	2.151ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	5.000s	119.917us	1	1	100.00
V2	reset_recovery	aes_alert_reset	3.000s	211.014us	50	50	100.00
V2	stress	aes_stress	4.000s	105.061us	50	50	100.00
V2	sideload	aes_stress	4.000s	105.061us	50	50	100.00
		aes_sideload	3.000s	126.027us	50	50	100.00
V2	deinitialization	aes_deinit	4.000s	406.500us	50	50	100.00
V2	stress_all	aes_stress_all	24.000s	4.686ms	10	10	100.00
V2	alert_test	aes_alert_test	3.000s	56.517us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	32.000s	246.209us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	32.000s	246.209us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	15.000s	77.365us	5	5	100.00
		aes_csr_rw	11.000s	113.781us	20	20	100.00
		aes_csr_aliasing	5.000s	1.465ms	5	5	100.00
		aes_same_csr_outstanding	3.000s	116.878us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	15.000s	77.365us	5	5	100.00
		aes_csr_rw	11.000s	113.781us	20	20	100.00
		aes_csr_aliasing	5.000s	1.465ms	5	5	100.00
		aes_same_csr_outstanding	3.000s	116.878us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	4.000s	120.504us	50	50	100.00
V2S	fault_inject	aes_fi	3.000s	95.317us	48	50	96.00
		aes_control_fi	37.000s	200.000ms	282	300	94.00
		aes_cipher_fi	44.000s	10.014ms	332	350	94.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	20.000s	280.195us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	20.000s	280.195us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	20.000s	280.195us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	20.000s	280.195us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	19.000s	239.363us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	1.180ms	5	5	100.00
		aes_tl_intg_err	27.000s	162.820us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	27.000s	162.820us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	3.000s	211.014us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	20.000s	280.195us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	201.385us	50	50	100.00
		aes_stress	4.000s	105.061us	50	50	100.00
		aes_alert_reset	3.000s	211.014us	50	50	100.00
		aes_core_fi	31.000s	10.003ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	20.000s	280.195us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	3.000s	60.555us	50	50	100.00
		aes_stress	4.000s	105.061us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	4.000s	105.061us	50	50	100.00
		aes_sideload	3.000s	126.027us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	3.000s	60.555us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	3.000s	60.555us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	3.000s	60.555us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	3.000s	60.555us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	3.000s	60.555us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	4.000s	105.061us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	4.000s	105.061us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	3.000s	95.317us	48	50	96.00
V2S	sec_cm_main_fsm_redun	aes_fi	3.000s	95.317us	48	50	96.00
		aes_control_fi	37.000s	200.000ms	282	300	94.00
		aes_cipher_fi	44.000s	10.014ms	332	350	94.86
		aes_ctr_fi	3.000s	110.613us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	3.000s	95.317us	48	50	96.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	3.000s	95.317us	48	50	96.00
		aes_control_fi	37.000s	200.000ms	282	300	94.00
		aes_cipher_fi	44.000s	10.014ms	332	350	94.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	44.000s	10.014ms	332	350	94.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	3.000s	95.317us	48	50	96.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	3.000s	95.317us	48	50	96.00
		aes_control_fi	37.000s	200.000ms	282	300	94.00
		aes_ctr_fi	3.000s	110.613us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	3.000s	95.317us	48	50	96.00
		aes_control_fi	37.000s	200.000ms	282	300	94.00
		aes_cipher_fi	44.000s	10.014ms	332	350	94.86
		aes_ctr_fi	3.000s	110.613us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	3.000s	211.014us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	3.000s	95.317us	48	50	96.00
		aes_control_fi	37.000s	200.000ms	282	300	94.00
		aes_cipher_fi	44.000s	10.014ms	332	350	94.86
		aes_ctr_fi	3.000s	110.613us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	3.000s	95.317us	48	50	96.00
		aes_control_fi	37.000s	200.000ms	282	300	94.00
		aes_cipher_fi	44.000s	10.014ms	332	350	94.86
		aes_ctr_fi	3.000s	110.613us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	3.000s	95.317us	48	50	96.00
		aes_control_fi	37.000s	200.000ms	282	300	94.00
		aes_ctr_fi	3.000s	110.613us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	3.000s	95.317us	48	50	96.00
		aes_control_fi	37.000s	200.000ms	282	300	94.00
		aes_cipher_fi	44.000s	10.014ms	332	350	94.86
V2S		TOTAL			944	985	95.84
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	23.000s	19.176ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1551	1602	96.82

Failure Buckets

Job timed out after * minutes has 18 failures:
- Test aes_control_fi has 9 failures.
  - 9.aes_control_fi.97703567327420752223250390695079301730706487074974932718024385003870556605544
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/9.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 24.aes_control_fi.63843002269900747329646223018218490895958831411296307866256491399279950380715
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/24.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 7 more failures.
- Test aes_cipher_fi has 9 failures.
  - 30.aes_cipher_fi.78450920035475560982383672388317364208344945676213830344393044023504407887628
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/30.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 45.aes_cipher_fi.108760002364192468057583553927741289657621574414528911904191309798061805366605
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/45.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 9 failures:

Test aes_stress_all_with_rand_reset has 9 failures.

0.aes_stress_all_with_rand_reset.114609087749673275227369659811212735591426870317501200137902538552436639576995
Line 392, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1071716901 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1071716901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.19987859567152445121025691596236013381959426700606490651869585807692987176346
Line 557, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 189454654 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 189454654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 18.aes_cipher_fi.12300557091035352838164968339051769423167434862616227521355298741518551654218
    Line 138, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/18.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10022911437 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022911437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 31.aes_cipher_fi.67212819566182943392747650327959212014371908552224286954752332858632433362450
    Line 140, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/31.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011831711 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011831711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 2.aes_control_fi.21727638887026376548882963020493763297500356383189495131583010585735314143970
    Line 133, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/2.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006176107 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006176107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 7.aes_control_fi.2933172326917177026334100323109557751839072391910863866834149779415737304730
    Line 131, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/7.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009525692 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009525692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 26.aes_core_fi.22345454828249533631517254341763903247128943447947905555023673736180255048270
    Line 136, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/26.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010585186 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010585186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 28.aes_core_fi.44319054504786682784975643041571922698345975897084912773182473126853151913095
    Line 138, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/28.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003273871 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003273871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 1.aes_core_fi.111768728548312157068210775191140012172568536134727543925625587510553105640841
    Line 140, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10019833287 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019833287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 2.aes_stress_all_with_rand_reset.88669520701533479382319528585344428576441323963088473918095084321604183559735
    Line 172, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  78795947 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  78795947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

39.aes_fi.54594824480809055327238601900419460550895578592210209639776916821053239286431
Line 2063, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/39.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 8282659 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 8271670 PS)
  UVM_ERROR @   8282659 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @   8282659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 42.aes_fi.95018712710245611457010143178071710276665498111957354539139753486641593006675
    Line 6309, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/42.aes_fi/latest/run.log
```
  UVM_FATAL @ 212022378 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 212022378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_control_fi has 1 failures.
  - 115.aes_control_fi.89755407581552625447356356859213017172930631606679693233625717494113625679154
    Line 140, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/115.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```