CSRNG Simulation Results

Sunday November 02 2025 00:09:31 UTC

GitHub Revision: 0136fdb

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	169.062us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	36.356us	5	5	100.00
V1	csr_rw	csrng_csr_rw	3.000s	17.386us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	13.000s	559.982us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	158.133us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	4.000s	25.104us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	3.000s	17.386us	20	20	100.00
		csrng_csr_aliasing	5.000s	158.133us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	19.000s	1.436ms	200	200	100.00
V2	alerts	csrng_alert	1.567m	6.181ms	500	500	100.00
V2	err	csrng_err	4.000s	111.139us	500	500	100.00
V2	cmds	csrng_cmds	8.600m	47.182ms	50	50	100.00
V2	life cycle	csrng_cmds	8.600m	47.182ms	50	50	100.00
V2	stress_all	csrng_stress_all	13.833m	27.189ms	48	50	96.00
V2	intr_test	csrng_intr_test	3.000s	63.882us	50	50	100.00
V2	alert_test	csrng_alert_test	4.000s	133.880us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	9.000s	372.684us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	9.000s	372.684us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	36.356us	5	5	100.00
		csrng_csr_rw	3.000s	17.386us	20	20	100.00
		csrng_csr_aliasing	5.000s	158.133us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	647.785us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	36.356us	5	5	100.00
		csrng_csr_rw	3.000s	17.386us	20	20	100.00
		csrng_csr_aliasing	5.000s	158.133us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	647.785us	20	20	100.00
V2		TOTAL			1438	1440	99.86
V2S	tl_intg_err	csrng_sec_cm	7.000s	287.026us	5	5	100.00
		csrng_tl_intg_err	14.000s	1.687ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	59.154us	50	50	100.00
		csrng_csr_rw	3.000s	17.386us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.567m	6.181ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	13.833m	27.189ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	19.000s	1.436ms	200	200	100.00
		csrng_err	4.000s	111.139us	500	500	100.00
		csrng_sec_cm	7.000s	287.026us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	19.000s	1.436ms	200	200	100.00
		csrng_err	4.000s	111.139us	500	500	100.00
		csrng_sec_cm	7.000s	287.026us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	19.000s	1.436ms	200	200	100.00
		csrng_err	4.000s	111.139us	500	500	100.00
		csrng_sec_cm	7.000s	287.026us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	19.000s	1.436ms	200	200	100.00
		csrng_err	4.000s	111.139us	500	500	100.00
		csrng_sec_cm	7.000s	287.026us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	19.000s	1.436ms	200	200	100.00
		csrng_err	4.000s	111.139us	500	500	100.00
		csrng_sec_cm	7.000s	287.026us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	19.000s	1.436ms	200	200	100.00
		csrng_err	4.000s	111.139us	500	500	100.00
		csrng_sec_cm	7.000s	287.026us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	19.000s	1.436ms	200	200	100.00
		csrng_err	4.000s	111.139us	500	500	100.00
		csrng_sec_cm	7.000s	287.026us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.567m	6.181ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	19.000s	1.436ms	200	200	100.00
		csrng_err	4.000s	111.139us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	13.833m	27.189ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.567m	6.181ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	14.000s	1.687ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	19.000s	1.436ms	200	200	100.00
		csrng_err	4.000s	111.139us	500	500	100.00
		csrng_sec_cm	7.000s	287.026us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	19.000s	1.436ms	200	200	100.00
		csrng_err	4.000s	111.139us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	19.000s	1.436ms	200	200	100.00
		csrng_err	4.000s	111.139us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	19.000s	1.436ms	200	200	100.00
		csrng_err	4.000s	111.139us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	19.000s	1.436ms	200	200	100.00
		csrng_err	4.000s	111.139us	500	500	100.00
		csrng_sec_cm	7.000s	287.026us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	19.000s	1.436ms	200	200	100.00
		csrng_err	4.000s	111.139us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	6.667m	32.826ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			1628	1630	99.88

Failure Buckets

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
  • Test csrng_stress_all has 2 failures.

    • 42.csrng_stress_all.57545615732722362618520270652072471382217787254025250632906254585268368115843
      Line 157, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/42.csrng_stress_all/latest/run.log

        UVM_ERROR @ 513044184 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 513044184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 44.csrng_stress_all.53280202003148329589926091549171476383016547732587401370457179436513302607089
      Line 150, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/44.csrng_stress_all/latest/run.log

        UVM_ERROR @  41534272 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @  41534272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---