EDN Simulation Results

Sunday November 02 2025 00:09:31 UTC

GitHub Revision: 0136fdb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.420s 19.182us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.270s 56.472us 5 5 100.00
V1 csr_rw edn_csr_rw 1.240s 13.822us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 4.930s 273.372us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.510s 83.786us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.960s 27.796us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.240s 13.822us 20 20 100.00
edn_csr_aliasing 1.510s 83.786us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 52.880s 2.254ms 300 300 100.00
V2 csrng_commands edn_genbits 52.880s 2.254ms 300 300 100.00
V2 genbits edn_genbits 52.880s 2.254ms 300 300 100.00
V2 interrupts edn_intr 1.520s 28.683us 50 50 100.00
V2 alerts edn_alert 1.750s 39.347us 200 200 100.00
V2 errs edn_err 1.710s 97.817us 100 100 100.00
V2 disable edn_disable 1.330s 14.244us 50 50 100.00
edn_disable_auto_req_mode 1.590s 38.153us 50 50 100.00
V2 stress_all edn_stress_all 6.480s 706.798us 50 50 100.00
V2 intr_test edn_intr_test 1.240s 28.094us 50 50 100.00
V2 alert_test edn_alert_test 2.080s 57.277us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.460s 86.478us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 3.460s 86.478us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.270s 56.472us 5 5 100.00
edn_csr_rw 1.240s 13.822us 20 20 100.00
edn_csr_aliasing 1.510s 83.786us 5 5 100.00
edn_same_csr_outstanding 1.640s 55.940us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.270s 56.472us 5 5 100.00
edn_csr_rw 1.240s 13.822us 20 20 100.00
edn_csr_aliasing 1.510s 83.786us 5 5 100.00
edn_same_csr_outstanding 1.640s 55.940us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 6.500s 512.948us 5 5 100.00
edn_tl_intg_err 2.970s 195.628us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.270s 39.001us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.750s 39.347us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 6.500s 512.948us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 6.500s 512.948us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 6.500s 512.948us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 6.500s 512.948us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.750s 39.347us 200 200 100.00
edn_sec_cm 6.500s 512.948us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.750s 39.347us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.970s 195.628us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 1.809m 20.774ms 26 50 52.00
V3 TOTAL 26 50 52.00
TOTAL 1106 1130 97.88

Failure Buckets