HMAC Simulation Results

Sunday November 02 2025 00:09:31 UTC

GitHub Revision: 0136fdb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 15.310s 1.043ms 10 10 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.210s 30.984us 5 5 100.00
V1 csr_rw hmac_csr_rw 1.340s 102.191us 20 20 100.00
V1 csr_bit_bash hmac_csr_bit_bash 11.560s 1.099ms 5 5 100.00
V1 csr_aliasing hmac_csr_aliasing 6.270s 473.559us 5 5 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 13.794m 286.793ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.340s 102.191us 20 20 100.00
hmac_csr_aliasing 6.270s 473.559us 5 5 100.00
V1 TOTAL 65 65 100.00
V2 long_msg hmac_long_msg 1.269m 92.925ms 10 10 100.00
V2 back_pressure hmac_back_pressure 1.901m 1.527ms 25 25 100.00
V2 test_vectors hmac_test_sha256_vectors 4.737m 20.055ms 30 30 100.00
hmac_test_sha384_vectors 9.380m 14.852ms 75 75 100.00
hmac_test_sha512_vectors 10.344m 26.125ms 75 75 100.00
hmac_test_hmac256_vectors 17.090s 355.292us 50 50 100.00
hmac_test_hmac384_vectors 17.380s 4.287ms 60 60 100.00
hmac_test_hmac512_vectors 20.780s 408.302us 75 75 100.00
V2 burst_wr hmac_burst_wr 49.350s 15.976ms 50 50 100.00
V2 datapath_stress hmac_datapath_stress 22.151m 124.182ms 10 10 100.00
V2 error hmac_error 1.331m 20.471ms 10 10 100.00
V2 wipe_secret hmac_wipe_secret 2.067m 7.833ms 10 10 100.00
V2 save_and_restore hmac_smoke 15.310s 1.043ms 10 10 100.00
hmac_long_msg 1.269m 92.925ms 10 10 100.00
hmac_back_pressure 1.901m 1.527ms 25 25 100.00
hmac_datapath_stress 22.151m 124.182ms 10 10 100.00
hmac_burst_wr 49.350s 15.976ms 50 50 100.00
hmac_stress_all 40.313m 188.845ms 50 50 100.00
V2 fifo_empty_status_interrupt hmac_smoke 15.310s 1.043ms 10 10 100.00
hmac_long_msg 1.269m 92.925ms 10 10 100.00
hmac_back_pressure 1.901m 1.527ms 25 25 100.00
hmac_datapath_stress 22.151m 124.182ms 10 10 100.00
hmac_wipe_secret 2.067m 7.833ms 10 10 100.00
hmac_test_sha256_vectors 4.737m 20.055ms 30 30 100.00
hmac_test_sha384_vectors 9.380m 14.852ms 75 75 100.00
hmac_test_sha512_vectors 10.344m 26.125ms 75 75 100.00
hmac_test_hmac256_vectors 17.090s 355.292us 50 50 100.00
hmac_test_hmac384_vectors 17.380s 4.287ms 60 60 100.00
hmac_test_hmac512_vectors 20.780s 408.302us 75 75 100.00
V2 wide_digest_configurable_key_length hmac_smoke 15.310s 1.043ms 10 10 100.00
hmac_long_msg 1.269m 92.925ms 10 10 100.00
hmac_back_pressure 1.901m 1.527ms 25 25 100.00
hmac_datapath_stress 22.151m 124.182ms 10 10 100.00
hmac_burst_wr 49.350s 15.976ms 50 50 100.00
hmac_error 1.331m 20.471ms 10 10 100.00
hmac_wipe_secret 2.067m 7.833ms 10 10 100.00
hmac_test_sha256_vectors 4.737m 20.055ms 30 30 100.00
hmac_test_sha384_vectors 9.380m 14.852ms 75 75 100.00
hmac_test_sha512_vectors 10.344m 26.125ms 75 75 100.00
hmac_test_hmac256_vectors 17.090s 355.292us 50 50 100.00
hmac_test_hmac384_vectors 17.380s 4.287ms 60 60 100.00
hmac_test_hmac512_vectors 20.780s 408.302us 75 75 100.00
hmac_stress_all 40.313m 188.845ms 50 50 100.00
V2 stress_all hmac_stress_all 40.313m 188.845ms 50 50 100.00
V2 alert_test hmac_alert_test 0.950s 15.986us 50 50 100.00
V2 intr_test hmac_intr_test 0.950s 45.462us 50 50 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.660s 327.469us 20 20 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.660s 327.469us 20 20 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.210s 30.984us 5 5 100.00
hmac_csr_rw 1.340s 102.191us 20 20 100.00
hmac_csr_aliasing 6.270s 473.559us 5 5 100.00
hmac_same_csr_outstanding 2.910s 589.912us 20 20 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.210s 30.984us 5 5 100.00
hmac_csr_rw 1.340s 102.191us 20 20 100.00
hmac_csr_aliasing 6.270s 473.559us 5 5 100.00
hmac_same_csr_outstanding 2.910s 589.912us 20 20 100.00
V2 TOTAL 670 670 100.00
V2S tl_intg_err hmac_sec_cm 1.490s 937.623us 5 5 100.00
hmac_tl_intg_err 4.640s 262.181us 20 20 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.640s 262.181us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 15.310s 1.043ms 10 10 100.00
V3 stress_reset hmac_stress_reset 9.180s 155.476us 25 25 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 7.521m 263.382ms 35 35 100.00
V3 TOTAL 60 60 100.00
Unmapped tests hmac_directed 1.130s 19.769us 1 1 100.00
TOTAL 821 821 100.00