I2C Simulation Results

Sunday November 02 2025 00:09:31 UTC

GitHub Revision: `0136fdb`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.204m	3.557ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	34.230s	1.415ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.070s	26.877us	5	5	100.00
V1	csr_rw	i2c_csr_rw	2.510s	2.853ms	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.320s	2.173ms	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.030s	144.159us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.670s	32.522us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	2.510s	2.853ms	20	20	100.00
		i2c_csr_aliasing	2.030s	144.159us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	8.490s	832.481us	1	50	2.00
V2	host_stress_all	i2c_host_stress_all	52.221m	53.522ms	6	50	12.00
V2	host_maxperf	i2c_host_perf	16.852m	30.596ms	49	50	98.00
V2	host_override	i2c_host_override	1.080s	71.670us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	4.888m	7.581ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.269m	14.106ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.710s	543.660us	50	50	100.00
		i2c_host_fifo_fmt_empty	26.170s	1.132ms	50	50	100.00
		i2c_host_fifo_reset_rx	12.940s	2.506ms	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.623m	20.475ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	44.320s	4.406ms	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	4.850s	299.427us	16	50	32.00
V2	target_glitch	i2c_target_glitch	2.610s	1.832ms	0	2	0.00
V2	target_stress_all	i2c_target_stress_all	18.807m	46.363ms	48	50	96.00
V2	target_maxperf	i2c_target_perf	7.790s	937.046us	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.140m	7.378ms	50	50	100.00
		i2c_target_intr_smoke	10.160s	1.374ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.170s	1.404ms	50	50	100.00
		i2c_target_fifo_reset_tx	2.430s	279.971us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	19.431m	64.801ms	50	50	100.00
		i2c_target_stress_rd	1.140m	7.378ms	50	50	100.00
		i2c_target_intr_stress_wr	7.746m	26.652ms	48	50	96.00
V2	target_timeout	i2c_target_timeout	9.830s	27.965ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	1.278m	6.447ms	47	50	94.00
V2	bad_address	i2c_target_bad_addr	8.530s	10.582ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	35.280s	10.046ms	30	50	60.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	4.550s	1.033ms	50	50	100.00
		i2c_target_fifo_watermarks_tx	2.050s	167.819us	50	50	100.00
V2	host_mode_config_perf	i2c_host_perf	16.852m	30.596ms	49	50	98.00
		i2c_host_perf_precise	7.858m	23.191ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	44.320s	4.406ms	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	24.480s	2.502ms	49	50	98.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	4.520s	2.414ms	50	50	100.00
		i2c_target_nack_acqfull_addr	3.550s	1.893ms	50	50	100.00
		i2c_target_nack_txstretch	2.080s	2.556ms	31	50	62.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	25.110s	685.021us	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	3.490s	2.324ms	50	50	100.00
V2	alert_test	i2c_alert_test	1.060s	31.038us	50	50	100.00
V2	intr_test	i2c_intr_test	1.120s	38.516us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.960s	285.072us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.960s	285.072us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.070s	26.877us	5	5	100.00
		i2c_csr_rw	2.510s	2.853ms	20	20	100.00
		i2c_csr_aliasing	2.030s	144.159us	5	5	100.00
		i2c_same_csr_outstanding	1.520s	28.469us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.070s	26.877us	5	5	100.00
		i2c_csr_rw	2.510s	2.853ms	20	20	100.00
		i2c_csr_aliasing	2.030s	144.159us	5	5	100.00
		i2c_same_csr_outstanding	1.520s	28.469us	20	20	100.00
V2		TOTAL			1615	1792	90.12
V2S	tl_intg_err	i2c_tl_intg_err	2.430s	661.124us	20	20	100.00
		i2c_sec_cm	1.390s	69.799us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.430s	661.124us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	32.780s	2.793ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.630s	1.006ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	22.880s	3.517ms	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1795	2042	87.90

Failure Buckets

UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 88 failures:

Test i2c_host_error_intr has 49 failures.

0.i2c_host_error_intr.14979328307562776045352187612226110164808753393630246201999603713777490790835
Line 115, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

  UVM_ERROR @ 155892924 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 155892924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_error_intr.50362188291362239053329423797880897382810016096079599262373623405178967802173
Line 115, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_error_intr/latest/run.log

  UVM_ERROR @ 111478024 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 111478024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 47 more failures.

Test i2c_target_stress_all_with_rand_reset has 3 failures.

0.i2c_target_stress_all_with_rand_reset.53061530623937360832364344798506157826877414682163593795025700601737326076289
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  32022439 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  32022439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_target_stress_all_with_rand_reset.40535828930057964396430767778231102860479243008377857820682510003999388888461
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  26387223 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  26387223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test i2c_host_mode_toggle has 9 failures.

0.i2c_host_mode_toggle.36256888544141832295857929036852730605634692402272010559836939637157102104878
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 108935694 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 108935694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.i2c_host_mode_toggle.38117243860918030375157875395525392716199523215902287604333159064700995461814
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  13753548 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  13753548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test i2c_host_stress_all has 27 failures.

1.i2c_host_stress_all.24647206157809481842635376494999090402346904967193933877088828298238486452948
Line 200, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 57161828275 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 57161828275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_host_stress_all.35326611451139644236656332529760673938690040257726948796498419475004278709362
Line 116, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 14278656184 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 14278656184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 25 more failures.

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 31 failures:
- Test i2c_target_unexp_stop has 31 failures.
  - 0.i2c_target_unexp_stop.96769660043107903539176592676916059341062317367507425488329126113394612920154
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 239921861 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 48 [0x30])
  UVM_INFO @ 239921861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.i2c_target_unexp_stop.62232657825734715114677737517113739773574648426359411655800495276509507477041
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  29401115 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 247 [0xf7])
  UVM_INFO @  29401115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 29 more failures.

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 22 failures:

Test i2c_host_stress_all has 15 failures.

11.i2c_host_stress_all.91810869784029902095449610628596100886827069232724903891941403988064784407145
Line 117, in log /nightly/current_run/scratch/master/i2c-sim-vcs/11.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 13158536240 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @1911865

12.i2c_host_stress_all.37501479667419089840863990779002021813419018528127652077254840971206224422467
Line 159, in log /nightly/current_run/scratch/master/i2c-sim-vcs/12.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 19290149542 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @21463575

... and 13 more failures.

Test i2c_host_mode_toggle has 7 failures.

14.i2c_host_mode_toggle.102468522639063452823894920355491137809342850755233944935025341267361889412698
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/14.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 162348161 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @24764

35.i2c_host_mode_toggle.89965928871687514293468375387734292317943668400880367392069508348374817562604
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/35.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 271685966 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @123262

... and 5 more failures.

UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 20 failures:
- Test i2c_target_hrst has 20 failures.
  - 3.i2c_target_hrst.90965865504788307806460578056077516254482747114325081630122680195646221598324
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10171683211 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10171683211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.i2c_target_hrst.19483446543809015816630596428772815012448422542703764435100278525440591772105
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/5.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10691300108 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10691300108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 18 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 19 failures:
- Test i2c_target_nack_txstretch has 19 failures.
  - 2.i2c_target_nack_txstretch.63010699619397219115533266132928846681656869073666144167920458532601899953756
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 2266712432 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 2266712432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 7.i2c_target_nack_txstretch.84172488520129122693318651288071944212239644386966657330703995743175898134385
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/7.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 383892550 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 383892550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 17 more failures.

UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.99082359939019624631221477269820488689805491344577968013128259601192578502775
Line 88, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 732850685 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 732850685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.61378274066575281161432506191562310491407733505358226755062780702865804879434
Line 87, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2253620273 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2253620273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 6 failures.

1.i2c_target_stress_all_with_rand_reset.31743302198544776977123610187752953753798502950600314879055163084048393786858
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 585291823 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 585291823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_stress_all_with_rand_reset.99907016948323616958840279814491011525679941057844497060937626521648701759776
Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1497426726 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1497426726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 15 failures:
- Test i2c_target_unexp_stop has 15 failures.
  - 5.i2c_target_unexp_stop.9127937434342343600805960018945958196552038695375579330977767273594390248729
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 969248337 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 969248337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.i2c_target_unexp_stop.49447549935728105749632605148712943643640946667728998531794281711504105352128
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 115192167 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 115192167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 13 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 13 failures:

Test i2c_host_mode_toggle has 13 failures.

3.i2c_host_mode_toggle.56699440265045941717636355986635942458861959048828519639062573310319130793821
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 202433087 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

6.i2c_host_mode_toggle.109825121644788410221732107285528053173137474490146322237502389848930302663614
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/6.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 446717025 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 11 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 4 failures:

Test i2c_target_unexp_stop has 4 failures.

4.i2c_target_unexp_stop.5025137649662117135604783620819886330673530711406902389285726034185698424975
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 577966782 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 577966782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.i2c_target_unexp_stop.9571606966267889177549766754609858645643445659120998730610819466685788066552
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/22.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 1030778741 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 1030778741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 4 failures:
- Test i2c_target_intr_stress_wr has 2 failures.
  - 8.i2c_target_intr_stress_wr.15244670434273574448293863279680026280107420118418208508379240106001686190699
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/8.i2c_target_intr_stress_wr/latest/run.log
```
  UVM_FATAL @ 31421023045 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 31421023045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 21.i2c_target_intr_stress_wr.94314198487099774393925623345253937204684637930002306796032732965691979912840
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/21.i2c_target_intr_stress_wr/latest/run.log
```
  UVM_FATAL @ 47904476091 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 47904476091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all has 2 failures.
  - 38.i2c_target_stress_all.100940679592127829834381232529725636500496671102839654914030279794775084229882
    Line 102, in log /nightly/current_run/scratch/master/i2c-sim-vcs/38.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 54999609584 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 54999609584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 49.i2c_target_stress_all.55948222744902562102056905393116741978603028596076053530375462765289621877893
    Line 86, in log /nightly/current_run/scratch/master/i2c-sim-vcs/49.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 19309728013 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 19309728013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
- Test i2c_host_mode_toggle has 3 failures.
  - 11.i2c_host_mode_toggle.22243100631894391437031387735298030667083040817127632621637634118525723820474
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/11.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  32293139 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0x2d3fa814, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  32293139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 28.i2c_host_mode_toggle.83192093992607703932786308726003752035649740218709476060652765278394923831669
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/28.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @ 137146109 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0xa7530994, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 137146109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 3 failures:
- Test i2c_target_stretch has 3 failures.
  - 17.i2c_target_stretch.2557767142039683282557771997820261342061399185417289031119138099891743439033
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/17.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10005285727 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10005285727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 25.i2c_target_stretch.113439943376458848957662967158515234068010390017360717553300315331931126029494
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/25.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10002339281 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10002339281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
Job timed out after * minutes has 2 failures:
- Test i2c_host_stress_all has 1 failures.
  - 0.i2c_host_stress_all.75751333729077936602465723992216268809491793113605816999569668827536375146528
    Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
- Test i2c_host_perf has 1 failures.
  - 20.i2c_host_perf.41300535014550924435543275387235309316547362762758829519020918258465419524202
    Log /nightly/current_run/scratch/master/i2c-sim-vcs/20.i2c_host_perf/latest/run.log
```
  Job timed out after 60 minutes
```

UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 2 failures:

Test i2c_target_glitch has 2 failures.

0.i2c_target_glitch.29286760633556598375411814399498785832342680039452566246710753528577392303459
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 504144195 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 504144195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_glitch.38591147615756235548654473525565341750805823552400647065871549664546753149251
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 1832067503 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 1832067503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Error-[NOA] Null object access has 2 failures:

Test i2c_host_mode_toggle has 2 failures.

43.i2c_host_mode_toggle.108537391650913134348253610051644551627580950090801145316819301846337832689788
Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/43.i2c_host_mode_toggle/latest/run.log

  Error-[NOA] Null object access
  src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.

47.i2c_host_mode_toggle.106217781837656690838872622015440249248224273416516048348483598915728303042014
Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/47.i2c_host_mode_toggle/latest/run.log

  Error-[NOA] Null object access
  src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.

UVM_ERROR (cip_base_vseq.sv:1142) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 9.i2c_target_stress_all_with_rand_reset.18612952318146388784312841372595187744187166810735034338495646264540181765684
    Line 89, in log /nightly/current_run/scratch/master/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 447332823 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 447332823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 13.i2c_host_stress_all.70537280602416909985637728145055212381207341308091000053587360072466916962333
    Line 129, in log /nightly/current_run/scratch/master/i2c-sim-vcs/13.i2c_host_stress_all/latest/run.log
```
  UVM_ERROR @ 53537945610 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @15443451
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test i2c_target_tx_stretch_ctrl has 1 failures.
  - 35.i2c_target_tx_stretch_ctrl.75794376605596948418268479861581216631365191518972328936864028796337370973887
    Line 121, in log /nightly/current_run/scratch/master/i2c-sim-vcs/35.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```