KEYMGR Simulation Results

Sunday November 02 2025 00:09:31 UTC

GitHub Revision: `0136fdb`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	18.260s	3.694ms	50	50	100.00
V1	random	keymgr_random	46.310s	7.742ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.500s	279.645us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.430s	17.135us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	19.720s	3.580ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	12.250s	1.717ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.540s	36.262us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.430s	17.135us	20	20	100.00
		keymgr_csr_aliasing	12.250s	1.717ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.578m	2.303ms	50	50	100.00
V2	sideload	keymgr_sideload	31.070s	4.669ms	50	50	100.00
		keymgr_sideload_kmac	42.120s	2.307ms	50	50	100.00
		keymgr_sideload_aes	38.710s	14.560ms	50	50	100.00
		keymgr_sideload_otbn	44.170s	4.653ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	16.820s	6.641ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	15.910s	1.424ms	48	50	96.00
V2	kmac_error_response	keymgr_kmac_rsp_err	7.390s	816.814us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	49.650s	6.381ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.024m	8.994ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	10.640s	1.634ms	50	50	100.00
V2	stress_all	keymgr_stress_all	1.953m	5.175ms	47	50	94.00
V2	intr_test	keymgr_intr_test	1.140s	16.560us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.400s	60.166us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.820s	538.175us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.820s	538.175us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.500s	279.645us	5	5	100.00
		keymgr_csr_rw	1.430s	17.135us	20	20	100.00
		keymgr_csr_aliasing	12.250s	1.717ms	5	5	100.00
		keymgr_same_csr_outstanding	3.420s	339.239us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.500s	279.645us	5	5	100.00
		keymgr_csr_rw	1.430s	17.135us	20	20	100.00
		keymgr_csr_aliasing	12.250s	1.717ms	5	5	100.00
		keymgr_same_csr_outstanding	3.420s	339.239us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	sec_cm_additional_check	keymgr_sec_cm	11.350s	1.760ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	11.350s	1.760ms	5	5	100.00
		keymgr_tl_intg_err	7.690s	288.696us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.880s	460.865us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.880s	460.865us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.880s	460.865us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.880s	460.865us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	12.450s	1.665ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	11.350s	1.760ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	11.350s	1.760ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	7.690s	288.696us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.880s	460.865us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.578m	2.303ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	46.310s	7.742ms	50	50	100.00
		keymgr_csr_rw	1.430s	17.135us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	46.310s	7.742ms	50	50	100.00
		keymgr_csr_rw	1.430s	17.135us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	46.310s	7.742ms	50	50	100.00
		keymgr_csr_rw	1.430s	17.135us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	15.910s	1.424ms	48	50	96.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.024m	8.994ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.024m	8.994ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	46.310s	7.742ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	24.550s	3.503ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	11.350s	1.760ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	11.350s	1.760ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	11.350s	1.760ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	25.690s	1.165ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	15.910s	1.424ms	48	50	96.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	11.350s	1.760ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	11.350s	1.760ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	11.350s	1.760ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	25.690s	1.165ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	25.690s	1.165ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	11.350s	1.760ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	25.690s	1.165ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	11.350s	1.760ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	25.690s	1.165ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	25.410s	2.895ms	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			1084	1110	97.66

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
- Test keymgr_stress_all_with_rand_reset has 21 failures.
  - 3.keymgr_stress_all_with_rand_reset.5857752018912602649105533407633840657248774373882974349531500396634820030220
    Line 414, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 546972242 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 546972242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.keymgr_stress_all_with_rand_reset.99510480043120402240529921642480945971279971686430894313662400294021274984701
    Line 1472, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1986099148 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1986099148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 19 more failures.

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StOwnerIntKey for Attestation Kmac has 1 failures:

Test keymgr_stress_all has 1 failures.

7.keymgr_stress_all.26743848095053445628445586653647023359411796104035003779831220643456344847769
Line 3857, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/7.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 499783448 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (12304493146104824885766228700275636298921519593355407160237764045820782993929728642170812958991380107890778853171294086008215141091864399560472330177253229 [0xeaef1c139e38624d3dae4265ee7784da305e10b88d38d519ae0c4e108f6b4c2e862f6e45d81e2ff4880f31866e7366536d31ce40274640ff2fd3c4de66828f6d] vs 12304493146104824885766228700275636298921519593355407160237764045820782993929728642170812958991380107890778853171294086008215141091864399560472330177253229 [0xeaef1c139e38624d3dae4265ee7784da305e10b88d38d519ae0c4e108f6b4c2e862f6e45d81e2ff4880f31866e7366536d31ce40274640ff2fd3c4de66828f6d]) KMAC key at state StOwnerIntKey for Attestation Kmac
  UVM_INFO @ 499783448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StOwnerKey for Attestation Aes has 1 failures:

Test keymgr_lc_disable has 1 failures.

15.keymgr_lc_disable.96477415028700765546097695733251314180445520029426137018496818026301042257687
Line 193, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/15.keymgr_lc_disable/latest/run.log

  UVM_ERROR @ 121900171 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (5106329596979561645428878133727115141035351731705892378747030095095462566181474881176867301701757308089400504215414480072198028745975437479417078241458191 [0x617f381a53ccfee5e5ab8553ebbc163b51d7ea70554a2467133fdc617b81a7dbd04e4e9121f18d23a2259f21121cf848247e919ecfa9e89df4db91c2f1ea780f] vs 5106329596979561645428878133727115141035351731705892378747030095095462566181474881176867301701757308089400504215414480072198028745975437479417078241458191 [0x617f381a53ccfee5e5ab8553ebbc163b51d7ea70554a2467133fdc617b81a7dbd04e4e9121f18d23a2259f21121cf848247e919ecfa9e89df4db91c2f1ea780f]) AES key at state StOwnerKey for Attestation Aes
  UVM_INFO @ 121900171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 25.keymgr_stress_all.44902966007222200959548813426362363493657613480655770410414829636491904155391
    Line 2599, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/25.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 581534642 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 581534642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StCreatorRootKey for Attestation Kmac has 1 failures:

Test keymgr_lc_disable has 1 failures.

29.keymgr_lc_disable.38058217852473191260061231397404827588543989699577630241123504751598281479980
Line 198, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/29.keymgr_lc_disable/latest/run.log

  UVM_ERROR @  89746799 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (2228387229292698228046437356086479788022016869011284084153203706503260111367430663903600210955101660746835500926877913606591396151681578498327793975029033 [0x2a8c214034ca4103b60eea40dee6bacc752a4a689141c6529cf4593316688c89f0b03ee8232061d4364d64d7e6fb47a5b7cac2edb396638193a403e0c3fded29] vs 2228387229292698228046437356086479788022016869011284084153203706503260111367430663903600210955101660746835500926877913606591396151681578498327793975029033 [0x2a8c214034ca4103b60eea40dee6bacc752a4a689141c6529cf4593316688c89f0b03ee8232061d4364d64d7e6fb47a5b7cac2edb396638193a403e0c3fded29]) KMAC key at state StCreatorRootKey for Attestation Kmac
  UVM_INFO @  89746799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:651) [scoreboard] Check failed act_state == addr_phase_working_state (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 45.keymgr_stress_all.70315448048687168980628542108271772903866208317677634872832689825475396893994
    Line 2779, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/45.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 1189925116 ps: (keymgr_scoreboard.sv:651) [uvm_test_top.env.scoreboard] Check failed act_state == addr_phase_working_state (1 [0x1] vs 6 [0x6])
  UVM_INFO @ 1189925116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```