KMAC/MASKED Simulation Results

Sunday November 02 2025 00:09:31 UTC

GitHub Revision: 0136fdb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.601m	19.207ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.560s	71.813us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.580s	119.594us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.490s	289.395us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.770s	1.016ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.210s	206.937us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.580s	119.594us	20	20	100.00
		kmac_csr_aliasing	10.770s	1.016ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.150s	21.731us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.970s	137.392us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	52.372m	457.868ms	50	50	100.00
V2	burst_write	kmac_burst_write	22.146m	389.127ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	37.658m	189.864ms	5	5	100.00
		kmac_test_vectors_sha3_256	32.782m	120.196ms	5	5	100.00
		kmac_test_vectors_sha3_384	28.870m	140.720ms	5	5	100.00
		kmac_test_vectors_sha3_512	25.590s	13.505ms	5	5	100.00
		kmac_test_vectors_shake_128	30.950m	43.251ms	5	5	100.00
		kmac_test_vectors_shake_256	34.805m	181.726ms	5	5	100.00
		kmac_test_vectors_kmac	3.200s	41.454us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.820s	164.747us	5	5	100.00
V2	sideload	kmac_sideload	7.815m	42.182ms	50	50	100.00
V2	app	kmac_app	6.271m	69.671ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.493m	67.950ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.002m	102.127ms	50	50	100.00
V2	error	kmac_error	7.761m	19.899ms	50	50	100.00
V2	key_error	kmac_key_error	20.690s	8.303ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	10.990s	367.715us	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	30.730s	5.843ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	40.890s	2.083ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	55.440s	22.055ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	35.740s	896.397us	50	50	100.00
V2	stress_all	kmac_stress_all	46.986m	121.453ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.250s	27.142us	50	50	100.00
V2	alert_test	kmac_alert_test	1.450s	567.781us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	5.160s	319.240us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	5.160s	319.240us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.560s	71.813us	5	5	100.00
		kmac_csr_rw	1.580s	119.594us	20	20	100.00
		kmac_csr_aliasing	10.770s	1.016ms	5	5	100.00
		kmac_same_csr_outstanding	3.160s	155.052us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.560s	71.813us	5	5	100.00
		kmac_csr_rw	1.580s	119.594us	20	20	100.00
		kmac_csr_aliasing	10.770s	1.016ms	5	5	100.00
		kmac_same_csr_outstanding	3.160s	155.052us	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.840s	57.332us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.840s	57.332us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.840s	57.332us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.840s	57.332us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.930s	478.256us	18	20	90.00
V2S	tl_intg_err	kmac_sec_cm	1.509m	38.269ms	5	5	100.00
		kmac_tl_intg_err	5.590s	734.775us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.590s	734.775us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	35.740s	896.397us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.601m	19.207ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.815m	42.182ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.840s	57.332us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.509m	38.269ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.509m	38.269ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.509m	38.269ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.601m	19.207ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	35.740s	896.397us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.509m	38.269ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.925m	5.307ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.601m	19.207ms	50	50	100.00
V2S		TOTAL			73	75	97.33
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.645m	24.010ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			936	940	99.57

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 2 failures:

  • Test kmac_stress_all_with_rand_reset has 2 failures.

    • 0.kmac_stress_all_with_rand_reset.4412681741936829110415278843416010481723868189732751696091116836800169493599
      Line 216, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4711815329 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 4711815329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.kmac_stress_all_with_rand_reset.89021719746857404569054080393355565113192222828523020023787154377049973210089
      Line 195, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1848280213 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 1848280213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 2 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 2 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.19021231273418820527461310974204197920242654616813396655849323192315938723542
      Line 207, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_ERROR @  88867000 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1270903048 [0x4bc07108] vs 0 [0x0]) Regname: kmac_reg_block.prefix_4.prefix_0 reset value: 0x0
        UVM_INFO @  88867000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 11.kmac_shadow_reg_errors_with_csr_rw.48378126231221106690617096686038491807913187454163866702040663790477887649013
      Line 194, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_ERROR @  87354883 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (101800964 [0x6115c04] vs 663603857 [0x278dca91]) Regname: kmac_reg_block.prefix_0.prefix_0 reset value: 0x0
        UVM_INFO @  87354883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---