OTBN Simulation Results

Sunday November 02 2025 00:09:31 UTC

GitHub Revision: 0136fdb

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 17.025s 0 1 0.00
V1 single_binary otbn_single 1.550m 438.469us 0 100 0.00
V1 csr_hw_reset otbn_csr_hw_reset 4.000s 55.943us 5 5 100.00
V1 csr_rw otbn_csr_rw 7.000s 29.476us 20 20 100.00
V1 csr_bit_bash otbn_csr_bit_bash 8.000s 268.859us 5 5 100.00
V1 csr_aliasing otbn_csr_aliasing 4.000s 30.122us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 8.000s 42.563us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 7.000s 29.476us 20 20 100.00
otbn_csr_aliasing 4.000s 30.122us 5 5 100.00
V1 mem_walk otbn_mem_walk 40.000s 1.200ms 5 5 100.00
V1 mem_partial_access otbn_mem_partial_access 18.000s 124.997us 5 5 100.00
V1 TOTAL 65 166 39.16
V2 reset_recovery otbn_reset 1.200m 1.336ms 0 10 0.00
V2 multi_error otbn_multi_err 53.000s 164.252us 0 1 0.00
V2 back_to_back otbn_multi 1.317m 1.125ms 0 10 0.00
V2 stress_all otbn_stress_all 1.633m 312.280us 0 10 0.00
V2 lc_escalation otbn_escalate 32.000s 107.888us 28 60 46.67
V2 zero_state_err_urnd otbn_zero_state_err_urnd 7.000s 37.436us 3 5 60.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 20.000s 176.419us 0 10 0.00
V2 alert_test otbn_alert_test 8.000s 51.696us 50 50 100.00
V2 intr_test otbn_intr_test 4.000s 65.434us 50 50 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 8.000s 616.467us 20 20 100.00
V2 tl_d_illegal_access otbn_tl_errors 8.000s 616.467us 20 20 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 4.000s 55.943us 5 5 100.00
otbn_csr_rw 7.000s 29.476us 20 20 100.00
otbn_csr_aliasing 4.000s 30.122us 5 5 100.00
otbn_same_csr_outstanding 6.000s 35.571us 20 20 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 4.000s 55.943us 5 5 100.00
otbn_csr_rw 7.000s 29.476us 20 20 100.00
otbn_csr_aliasing 4.000s 30.122us 5 5 100.00
otbn_same_csr_outstanding 6.000s 35.571us 20 20 100.00
V2 TOTAL 171 246 69.51
V2S mem_integrity otbn_imem_err 15.000s 56.085us 2 10 20.00
otbn_dmem_err 16.000s 52.183us 0 15 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 12.000s 128.079us 0 5 0.00
otbn_controller_ispr_rdata_err 17.000s 41.922us 0 5 0.00
otbn_mac_bignum_acc_err 11.000s 27.462us 0 5 0.00
otbn_urnd_err 5.000s 27.125us 2 2 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 6.000s 114.717us 5 5 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 6.000s 39.237us 1 2 50.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 8.000s 35.017us 9 10 90.00
V2S tl_intg_err otbn_sec_cm 4.600m 1.748ms 4 5 80.00
otbn_tl_intg_err 33.000s 203.706us 20 20 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 1.217m 411.982us 16 20 80.00
V2S prim_fsm_check otbn_sec_cm 4.600m 1.748ms 4 5 80.00
V2S prim_count_check otbn_sec_cm 4.600m 1.748ms 4 5 80.00
V2S sec_cm_mem_scramble otbn_smoke 17.025s 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 16.000s 52.183us 0 15 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 15.000s 56.085us 2 10 20.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 33.000s 203.706us 20 20 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 32.000s 107.888us 28 60 46.67
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 15.000s 56.085us 2 10 20.00
otbn_dmem_err 16.000s 52.183us 0 15 0.00
otbn_zero_state_err_urnd 7.000s 37.436us 3 5 60.00
otbn_illegal_mem_acc 6.000s 114.717us 5 5 100.00
otbn_sec_cm 4.600m 1.748ms 4 5 80.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 4.600m 1.748ms 4 5 80.00
V2S sec_cm_scramble_key_sideload otbn_single 1.550m 438.469us 0 100 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 15.000s 56.085us 2 10 20.00
otbn_dmem_err 16.000s 52.183us 0 15 0.00
otbn_zero_state_err_urnd 7.000s 37.436us 3 5 60.00
otbn_illegal_mem_acc 6.000s 114.717us 5 5 100.00
otbn_sec_cm 4.600m 1.748ms 4 5 80.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 4.600m 1.748ms 4 5 80.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 32.000s 107.888us 28 60 46.67
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 15.000s 56.085us 2 10 20.00
otbn_dmem_err 16.000s 52.183us 0 15 0.00
otbn_zero_state_err_urnd 7.000s 37.436us 3 5 60.00
otbn_illegal_mem_acc 6.000s 114.717us 5 5 100.00
otbn_sec_cm 4.600m 1.748ms 4 5 80.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 4.600m 1.748ms 4 5 80.00
V2S sec_cm_data_reg_sw_sca otbn_single 1.550m 438.469us 0 100 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 12.000s 105.548us 0 12 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 7.000s 56.747us 5 5 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 37.000s 978.008us 0 5 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 37.000s 978.008us 0 5 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 14.000s 47.308us 0 10 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 4.600m 1.748ms 4 5 80.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 4.600m 1.748ms 4 5 80.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 14.000s 86.685us 0 10 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 4.600m 1.748ms 4 5 80.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 4.600m 1.748ms 4 5 80.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 9.000s 419.994us 0 5 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 9.000s 419.994us 0 5 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 35.000s 108.943us 5 7 71.43
V2S sec_cm_data_mem_sec_wipe otbn_single 1.550m 438.469us 0 100 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 1.550m 438.469us 0 100 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 1.550m 438.469us 0 100 0.00
V2S sec_cm_write_mem_integrity otbn_multi 1.317m 1.125ms 0 10 0.00
V2S sec_cm_ctrl_flow_count otbn_single 1.550m 438.469us 0 100 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 1.550m 438.469us 0 100 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 20.000s 215.563us 0 5 0.00
V2S sec_cm_key_sideload otbn_single 1.550m 438.469us 0 100 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 4.600m 1.748ms 4 5 80.00
V2S TOTAL 69 163 42.33
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 9.167m 3.699ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 305 585 52.14

Failure Buckets