0136fdb| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 8.000s | 193.088us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 2.000s | 49.608us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 2.000s | 42.939us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 4.000s | 189.944us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 2.000s | 16.311us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 2.000s | 89.316us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 2.000s | 42.939us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 2.000s | 16.311us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 58.933m | 600.000ms | 26 | 50 | 52.00 |
| V2 | cnt_rollover | cnt_rollover | 1.250m | 10.517ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 3.000s | 112.534us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 2.912h | 1.344s | 24 | 50 | 48.00 |
| V2 | alert_test | pattgen_alert_test | 2.000s | 21.900us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 2.000s | 23.400us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 3.000s | 46.012us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 3.000s | 46.012us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 2.000s | 49.608us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 2.000s | 42.939us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 2.000s | 16.311us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 2.000s | 33.078us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 2.000s | 49.608us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 2.000s | 42.939us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 2.000s | 16.311us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 2.000s | 33.078us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 290 | 340 | 85.29 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 2.000s | 84.952us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 2.000s | 72.748us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 2.000s | 84.952us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 2.817m | 5.459ms | 2 | 50 | 4.00 |
| V3 | TOTAL | 2 | 50 | 4.00 | |||
| Unmapped tests | pattgen_inactive_level | 3.933m | 10.008ms | 38 | 50 | 76.00 | |
| TOTAL | 460 | 570 | 80.70 |
UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 48 failures:
0.pattgen_stress_all_with_rand_reset.3344857106937730461578633527594443897773931743634172453482443398662270843051
Line 122, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1467041528 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1467055125 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1467055125 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1467175125 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
1.pattgen_stress_all_with_rand_reset.69362536542931865041783283479907872999794536502374846053133530534730964535469
Line 121, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2797930007 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 2797951259 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2797951259 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 2798191259 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
... and 46 more failures.
Job timed out after * minutes has 19 failures:
1.pattgen_perf.25552412278254824699821239847789098069677763290469279308929484585236735597298
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_perf/latest/run.log
Job timed out after 60 minutes
4.pattgen_perf.52095324928718056830619590204856918156963326141836366508884215643228059611427
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/4.pattgen_perf/latest/run.log
Job timed out after 60 minutes
... and 7 more failures.
5.pattgen_stress_all.102690955038721575240250424792622079689496537398062484921973129626292862220993
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/5.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
6.pattgen_stress_all.93246294358374926407673739289988611509534656127101184145274469107096071273379
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/6.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
... and 8 more failures.
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 16 failures:
0.pattgen_stress_all.103461552397949943091682887586673069528481811755757235347315147722067963206144
Line 122, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
UVM_ERROR @ 824731605 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10175
2.pattgen_stress_all.68591683529091072229911534784813560332060699836126594181232485282133340210399
Line 133, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/2.pattgen_stress_all/latest/run.log
UVM_ERROR @ 34078088 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10190
... and 14 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 15 failures:
0.pattgen_perf.112545302807532247210074193084307888049797214113332376379078784641368629177902
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.pattgen_perf.75014690420677730762415121907174138017756087843116377775304045895831979151295
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/5.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 3 failures:
25.pattgen_inactive_level.98431554115519559752078731707042491384329196436768175733692537727358106800499
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/25.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10012937305 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x2a446650, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
UVM_INFO @ 10012937305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.pattgen_inactive_level.2621780730069267101664529941612416636540032514232135270446364422802598544411
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/28.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10007697625 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xc0cc6950, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
UVM_INFO @ 10007697625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 2 failures:
19.pattgen_inactive_level.43778838501161604600934743782360068374436005426122291825202128371178303053751
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/19.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10034557948 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x8e4c610, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10034557948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.pattgen_inactive_level.34003026579500654551966497298261578439905762313293564524604744750386749880510
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/38.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10028103334 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x5b310ad0, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10028103334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 2 failures:
22.pattgen_inactive_level.101497826507559402011083560051716753779865867303277688526071874776197397307615
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/22.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10199452128 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x61357550, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10199452128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.pattgen_inactive_level.82518492667889029767668280705056702733365011331524550863680868868876303269730
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/35.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10009507771 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x105b96d0, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10009507771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
0.pattgen_inactive_level.94857782601246104071424166349835931439323057722891551918006484327726759710395
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10007564361 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xfbe8ea10, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10007564361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
1.pattgen_inactive_level.47294310620981740228409290557632440928240678093262664368576308788290026146013
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10528890095 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xb7b81050, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
UVM_INFO @ 10528890095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
2.pattgen_inactive_level.41089145906123935275219781934468254031602423778496223902644809749334521415662
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/2.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10095337044 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xc4dcdbd0, Comparison=CompareOpEq, exp_data=0x0, call_count=16)
UVM_INFO @ 10095337044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=25) has 1 failures:
21.pattgen_inactive_level.98162320989940531247947490729610455320641770037089847980663994207956650618842
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/21.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10059191111 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x41dc3e90, Comparison=CompareOpEq, exp_data=0x0, call_count=25)
UVM_INFO @ 10059191111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 1 failures:
26.pattgen_inactive_level.45496617754692778689647449349940100333291011972898586981179981285624355134177
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/26.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10054190342 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x53944390, Comparison=CompareOpEq, exp_data=0x0, call_count=23)
UVM_INFO @ 10054190342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---