0136fdb| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 7.000s | 178.996us | 2 | 2 | 100.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 9.660s | 563.442us | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 7.010s | 170.117us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 5.170s | 169.514us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 5.560s | 128.469us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 7.450s | 547.650us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 7.010s | 170.117us | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 5.560s | 128.469us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 6.850s | 172.485us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 4.950s | 128.167us | 5 | 5 | 100.00 |
| V1 | TOTAL | 67 | 67 | 100.00 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 5.470s | 135.462us | 2 | 2 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 24.940s | 587.248us | 20 | 20 | 100.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 8.070s | 312.293us | 2 | 2 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 7.780s | 1.052ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 9.940s | 180.903us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 9.940s | 180.903us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 9.660s | 563.442us | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 7.010s | 170.117us | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 5.560s | 128.469us | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 6.740s | 1.564ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 9.660s | 563.442us | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 7.010s | 170.117us | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 5.560s | 128.469us | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 6.740s | 1.564ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 114 | 114 | 100.00 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 1.877m | 6.764ms | 17 | 20 | 85.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 31.220s | 6.033ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 5.266m | 3.301ms | 1 | 5 | 20.00 |
| rom_ctrl_tl_intg_err | 1.026m | 785.434us | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 5.266m | 3.301ms | 1 | 5 | 20.00 |
| V2S | prim_count_check | rom_ctrl_sec_cm | 5.266m | 3.301ms | 1 | 5 | 20.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.877m | 6.764ms | 17 | 20 | 85.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.877m | 6.764ms | 17 | 20 | 85.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 1.877m | 6.764ms | 17 | 20 | 85.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.877m | 6.764ms | 17 | 20 | 85.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.877m | 6.764ms | 17 | 20 | 85.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 5.266m | 3.301ms | 1 | 5 | 20.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 5.266m | 3.301ms | 1 | 5 | 20.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 7.000s | 178.996us | 2 | 2 | 100.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 7.000s | 178.996us | 2 | 2 | 100.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 7.000s | 178.996us | 2 | 2 | 100.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 1.026m | 785.434us | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 1.877m | 6.764ms | 17 | 20 | 85.00 |
| rom_ctrl_kmac_err_chk | 8.070s | 312.293us | 2 | 2 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 1.877m | 6.764ms | 17 | 20 | 85.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.877m | 6.764ms | 17 | 20 | 85.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 1.877m | 6.764ms | 17 | 20 | 85.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 31.220s | 6.033ms | 20 | 20 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 5.266m | 3.301ms | 1 | 5 | 20.00 |
| V2S | TOTAL | 58 | 65 | 89.23 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 12.233m | 12.537ms | 20 | 20 | 100.00 |
| V3 | TOTAL | 20 | 20 | 100.00 | |||
| TOTAL | 259 | 266 | 97.37 |
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 3 failures:
0.rom_ctrl_corrupt_sig_fatal_chk.45976812264507905489123750028163965480116483238857278142505538394598167619715
Line 104, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_ERROR @ 1785659142 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 1785659142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.rom_ctrl_corrupt_sig_fatal_chk.78805206294172526364444091843151135404123934880771182920392281105122468561175
Line 89, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_ERROR @ 1379141272 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 1379141272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 2 failures:
0.rom_ctrl_sec_cm.89209842531992443608983346289711360438229916351793554572714921237993094495385
Line 221, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 13284417ps failed at 13284417ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 13284417ps failed at 13284417ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
4.rom_ctrl_sec_cm.96199622615507918011982929181069236407758824964388684658439743436070356008061
Line 115, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_sec_cm/latest/run.log
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 41238359ps failed at 41238359ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 41238359ps failed at 41238359ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:
1.rom_ctrl_sec_cm.85997139902221146917196272094199487712132174929168888679948619434742205306222
Line 304, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 42997898ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 42997898ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
Starting assertion attempts at time 42997898ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' has 1 failures:
3.rom_ctrl_sec_cm.80898327673744689498718489106288987669303807902021735300402826011202909823522
Line 429, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_sec_cm/latest/run.log
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 49035010ps failed at 49035010ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 290: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respOpcode_A: started at 49045214ps failed at 49045214ps
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'