ROM_CTRL/64KB Simulation Results

Sunday November 02 2025 00:09:31 UTC

GitHub Revision: 0136fdb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	12.410s	559.402us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	20.390s	308.171us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	14.070s	2.129ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	12.760s	2.054ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	8.920s	371.312us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	12.380s	311.575us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	14.070s	2.129ms	20	20	100.00
		rom_ctrl_csr_aliasing	8.920s	371.312us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	13.760s	1.077ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	9.920s	545.918us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	11.270s	231.323us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	1.076m	4.027ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	14.610s	1.321ms	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	12.040s	297.724us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	16.990s	3.982ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	16.990s	3.982ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	20.390s	308.171us	5	5	100.00
		rom_ctrl_csr_rw	14.070s	2.129ms	20	20	100.00
		rom_ctrl_csr_aliasing	8.920s	371.312us	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.820s	310.930us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	20.390s	308.171us	5	5	100.00
		rom_ctrl_csr_rw	14.070s	2.129ms	20	20	100.00
		rom_ctrl_csr_aliasing	8.920s	371.312us	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.820s	310.930us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	3.764m	13.646ms	20	20	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	53.760s	3.820ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	10.192m	2.469ms	0	5	0.00
		rom_ctrl_tl_intg_err	2.306m	852.339us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	10.192m	2.469ms	0	5	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	10.192m	2.469ms	0	5	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.764m	13.646ms	20	20	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.764m	13.646ms	20	20	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.764m	13.646ms	20	20	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.764m	13.646ms	20	20	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.764m	13.646ms	20	20	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	10.192m	2.469ms	0	5	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	10.192m	2.469ms	0	5	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	12.410s	559.402us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	12.410s	559.402us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	12.410s	559.402us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.306m	852.339us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.764m	13.646ms	20	20	100.00
		rom_ctrl_kmac_err_chk	14.610s	1.321ms	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	3.764m	13.646ms	20	20	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.764m	13.646ms	20	20	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	3.764m	13.646ms	20	20	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	53.760s	3.820ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	10.192m	2.469ms	0	5	0.00
V2S		TOTAL			60	65	92.31
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	5.386m	19.777ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			261	266	98.12

Failure Buckets

• Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' has 4 failures:
  • Test rom_ctrl_sec_cm has 4 failures.

    • 0.rom_ctrl_sec_cm.37950715337535016121375586735249559171287871039987423991083822583231078932478
      Line 300, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 101121769ps failed at 101121769ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 101184269ps failed at 101184269ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
      

    • 1.rom_ctrl_sec_cm.103297750626333873314688644168545501281000408762870878749841732862481777697015
      Line 107, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 8116772ps failed at 8116772ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 8134013ps failed at 8134013ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
      

    • ... and 2 more failures.

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:
  • Test rom_ctrl_sec_cm has 1 failures.

    • 3.rom_ctrl_sec_cm.45464351485654088647546544956959977068579927431178287663978176783915482901823
      Line 120, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 34712874ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 34712874ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
        Starting assertion attempts at time 34712874ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))