0136fdb| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 3.490s | 465.604us | 20 | 20 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.920s | 14.855us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 1.000s | 19.463us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.200s | 1.040ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 1.070s | 23.173us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.390s | 105.357us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 1.000s | 19.463us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 1.070s | 23.173us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 75 | 75 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 1.830s | 911.943us | 1 | 20 | 5.00 |
| V2 | disabled | rv_timer_disabled | 6.360s | 2.653ms | 20 | 20 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 11.233m | 510.936ms | 10 | 10 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 11.233m | 510.936ms | 10 | 10 | 100.00 |
| V2 | stress | rv_timer_stress_all | 9.500s | 5.071ms | 20 | 20 | 100.00 |
| V2 | alert_test | rv_timer_alert_test | 0.940s | 27.153us | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.890s | 11.744us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.180s | 1.003ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.180s | 1.003ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.920s | 14.855us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 1.000s | 19.463us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 1.070s | 23.173us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 1.150s | 55.338us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.920s | 14.855us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 1.000s | 19.463us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 1.070s | 23.173us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 1.150s | 55.338us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 191 | 210 | 90.95 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 1.100s | 868.473us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.750s | 150.748us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.750s | 150.748us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | min_value | rv_timer_min | 3.510s | 1.053ms | 2 | 10 | 20.00 |
| V3 | max_value | rv_timer_max | 2.330s | 80.581us | 0 | 10 | 0.00 |
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 1.020m | 7.216ms | 15 | 20 | 75.00 |
| V3 | TOTAL | 17 | 40 | 42.50 | |||
| TOTAL | 308 | 350 | 88.00 |
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 27 failures:
0.rv_timer_min.83243457249215595424209544139889880297565251159573675227769727923963310447844
Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
UVM_FATAL @ 67134314 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xf862cb04) == 0x1
UVM_INFO @ 67134314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rv_timer_min.111290986787281605465714998285708915092489763780701862496861168614523070081800
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/3.rv_timer_min/latest/run.log
UVM_FATAL @ 236571874 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x50e5f504) == 0x1
UVM_INFO @ 236571874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
0.rv_timer_random_reset.61222145577933712846579529572279034640808086885407111774349602451815005798225
Line 74, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 132158557 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xeacf2f04) == 0x1
UVM_INFO @ 132158557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_random_reset.78659595312043283670852979328023184004200069800019625935216724536857650379316
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 218662004 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xb3c20d04) == 0x1
UVM_INFO @ 218662004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 8 failures:
0.rv_timer_max.97901568002264618432602410899203599748545868164751517817263370549158991594311
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
UVM_ERROR @ 160161575 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 160161575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_max.110638128570804263529131086197686439323015683520809736973763500072147165666600
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_max/latest/run.log
UVM_ERROR @ 170499633 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 170499633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 3 failures:
11.rv_timer_stress_all_with_rand_reset.42083207295006914851263399917190129716359755917539895442551741744948544016106
Line 321, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/11.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 8850958853 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 8850958853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.rv_timer_stress_all_with_rand_reset.4688147272499854042750358898925984256469824915228397624061407887461492402308
Line 221, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/15.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 6460649401 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 6460649401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:
1.rv_timer_stress_all_with_rand_reset.8371640776908153498289865422626336564307222618228843710158565353784653172126
Line 109, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 781723803 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 781723803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.rv_timer_stress_all_with_rand_reset.32562564975859829847861679070229963450659711097688050302388113670032854448315
Line 193, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/18.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7583099540 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 7583099540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:365) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) has 2 failures:
5.rv_timer_max.9541798796182234828279616034836293737208570754423187288066177721106123717671
Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/5.rv_timer_max/latest/run.log
UVM_ERROR @ 88689639 ps: (rv_timer_scoreboard.sv:365) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (0x0 [0] vs 0x1 [1])
UVM_INFO @ 88689639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.rv_timer_max.88603338802380806103687041384833875856366079468308242016550492539887757228717
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/6.rv_timer_max/latest/run.log
UVM_ERROR @ 80580782 ps: (rv_timer_scoreboard.sv:365) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (0x0 [0] vs 0x1 [1])
UVM_INFO @ 80580782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---