SPI_DEVICE/1R1W Simulation Results

Sunday November 02 2025 00:09:31 UTC

GitHub Revision: 0136fdb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	7.707m	119.629ms	49	50	98.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.490s	21.830us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.760s	366.353us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	30.630s	2.714ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.710s	305.131us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.900s	207.347us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.760s	366.353us	20	20	100.00
		spi_device_csr_aliasing	15.710s	305.131us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.040s	11.522us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.670s	339.269us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	csb_read	spi_device_csb_read	1.200s	48.780us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.120s	6.738us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.080s	5.222us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	8.110s	447.704us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.110s	447.704us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	25.380s	15.045ms	50	50	100.00
		spi_device_tpm_sts_read	1.400s	90.953us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	52.660s	32.303ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	46.190s	51.977ms	50	50	100.00
		spi_device_flash_all	7.239m	187.496ms	49	50	98.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	34.230s	28.489ms	50	50	100.00
		spi_device_flash_all	7.239m	187.496ms	49	50	98.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	34.230s	28.489ms	50	50	100.00
		spi_device_flash_all	7.239m	187.496ms	49	50	98.00
V2	cmd_info_slots	spi_device_flash_all	7.239m	187.496ms	49	50	98.00
V2	cmd_read_status	spi_device_intercept	33.110s	13.552ms	50	50	100.00
		spi_device_flash_all	7.239m	187.496ms	49	50	98.00
V2	cmd_read_jedec	spi_device_intercept	33.110s	13.552ms	50	50	100.00
		spi_device_flash_all	7.239m	187.496ms	49	50	98.00
V2	cmd_read_sfdp	spi_device_intercept	33.110s	13.552ms	50	50	100.00
		spi_device_flash_all	7.239m	187.496ms	49	50	98.00
V2	cmd_fast_read	spi_device_intercept	33.110s	13.552ms	50	50	100.00
		spi_device_flash_all	7.239m	187.496ms	49	50	98.00
V2	cmd_read_pipeline	spi_device_intercept	33.110s	13.552ms	50	50	100.00
		spi_device_flash_all	7.239m	187.496ms	49	50	98.00
V2	flash_cmd_upload	spi_device_upload	38.580s	8.871ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.838m	16.727ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.838m	16.727ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.838m	16.727ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	50.750s	18.597ms	50	50	100.00
		spi_device_read_buffer_direct	23.880s	22.602ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.838m	16.727ms	50	50	100.00
		spi_device_flash_all	7.239m	187.496ms	49	50	98.00
V2	quad_spi	spi_device_flash_all	7.239m	187.496ms	49	50	98.00
V2	dual_spi	spi_device_flash_all	7.239m	187.496ms	49	50	98.00
V2	4b_3b_feature	spi_device_cfg_cmd	21.770s	2.419ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	21.770s	2.419ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	7.707m	119.629ms	49	50	98.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	5.550m	71.432ms	50	50	100.00
V2	stress_all	spi_device_stress_all	11.331m	381.806ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.160s	79.130us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.150s	49.827us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.080s	218.276us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.080s	218.276us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.490s	21.830us	5	5	100.00
		spi_device_csr_rw	2.760s	366.353us	20	20	100.00
		spi_device_csr_aliasing	15.710s	305.131us	5	5	100.00
		spi_device_same_csr_outstanding	4.860s	3.091ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.490s	21.830us	5	5	100.00
		spi_device_csr_rw	2.760s	366.353us	20	20	100.00
		spi_device_csr_aliasing	15.710s	305.131us	5	5	100.00
		spi_device_same_csr_outstanding	4.860s	3.091ms	20	20	100.00
V2		TOTAL			939	961	97.71
V2S	tl_intg_err	spi_device_sec_cm	1.800s	460.845us	5	5	100.00
		spi_device_tl_intg_err	16.740s	861.123us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	16.740s	861.123us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	5.132m	1.190s	49	50	98.00
		TOTAL			1127	1151	97.91

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 20 failures:

  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.78807893190194273328095135759251251657016662476061384893452062942384837825427
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1713096 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[88])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1713096 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1713096 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[984])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.16030719915214889470840606006390602815404061083690893028814317343102312257602
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1882177 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[93])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1882177 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1882177 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[989])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

• UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == gmv(csr) (* [] vs * []) CSR last_read_addr compare mismatch act * != exp *` has 2 failures:

  • Test spi_device_flash_all has 1 failures.

    • 1.spi_device_flash_all.41199656994356899028198229036811792125296872747435795236380210640079463729565
      Line 91, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_flash_all/latest/run.log

        UVM_ERROR @ 1409503205 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (9795584 [0x957800] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0x957800 != exp 0x0
        UVM_INFO @ 1472402132 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 5/7
        UVM_INFO @ 1472402132 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 6/7
        tl_ul_fuzzy_flash_status_q[i] = 0xacfd8
        UVM_INFO @ 1729766595 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 6/7
      

  • Test spi_device_flash_and_tpm has 1 failures.

    • 41.spi_device_flash_and_tpm.7236418992333565305026556144925589303143828402901306153811321857695721833371
      Line 94, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/41.spi_device_flash_and_tpm/latest/run.log

        UVM_ERROR @ 10304250939 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (15900672 [0xf2a000] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0xf2a000 != exp 0x0
        UVM_INFO @ 12529024203 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 2/12
        UVM_INFO @ 12529024203 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 3/12
        UVM_INFO @ 15049126403 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 3/12
        UVM_INFO @ 15049126403 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 4/12
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.86015167171375908418609327324180283796865043833892879033827112035446503030503
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   2042672 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x42d4cd [10000101101010011001101] vs 0x0 [0])
        UVM_ERROR @   2142672 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8e5de5 [100011100101110111100101] vs 0x0 [0])
        UVM_ERROR @   2241672 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd9617 [11011001011000010111] vs 0x0 [0])
        UVM_ERROR @   2321672 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x72f82f [11100101111100000101111] vs 0x0 [0])
        UVM_ERROR @   2392672 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x90ac08 [100100001010110000001000] vs 0x0 [0])
      

• UVM_ERROR (spi_device_pass_base_vseq.sv:705) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 5.spi_device_flash_mode_ignore_cmds.99457747100909251192964060724785853725912428927320388680852181408937598118035
      Line 111, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/5.spi_device_flash_mode_ignore_cmds/latest/run.log

        UVM_ERROR @ 6378575524 ps: (spi_device_pass_base_vseq.sv:705) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
        tl_ul_fuzzy_flash_status_q[i] = 0xa71dd0
        UVM_INFO @ 7230863213 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 8/10
        UVM_INFO @ 7230863213 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 9/10
        tl_ul_fuzzy_flash_status_q[i] = 0xa71dd0