SPI_DEVICE/2P Simulation Results

Sunday November 02 2025 00:09:31 UTC

GitHub Revision: 0136fdb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 8.933m 146.251ms 50 50 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.880s 43.394us 5 5 100.00
V1 csr_rw spi_device_csr_rw 2.980s 596.724us 20 20 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 28.070s 1.803ms 5 5 100.00
V1 csr_aliasing spi_device_csr_aliasing 18.500s 3.775ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 4.050s 58.774us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 2.980s 596.724us 20 20 100.00
spi_device_csr_aliasing 18.500s 3.775ms 5 5 100.00
V1 mem_walk spi_device_mem_walk 1.090s 28.757us 5 5 100.00
V1 mem_partial_access spi_device_mem_partial_access 2.630s 72.315us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 csb_read spi_device_csb_read 1.210s 26.460us 50 50 100.00
V2 mem_parity spi_device_mem_parity 1.470s 113.200us 20 20 100.00
V2 mem_cfg spi_device_ram_cfg 0.890s 108.144us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 8.220s 538.390us 50 50 100.00
V2 tpm_write spi_device_tpm_rw 8.220s 538.390us 50 50 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 36.370s 13.560ms 50 50 100.00
spi_device_tpm_sts_read 1.560s 162.866us 50 50 100.00
V2 tpm_fully_random_case spi_device_tpm_all 49.300s 9.060ms 50 50 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 34.860s 39.571ms 50 50 100.00
spi_device_flash_all 6.238m 169.466ms 50 50 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 34.500s 20.052ms 50 50 100.00
spi_device_flash_all 6.238m 169.466ms 50 50 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 34.500s 20.052ms 50 50 100.00
spi_device_flash_all 6.238m 169.466ms 50 50 100.00
V2 cmd_info_slots spi_device_flash_all 6.238m 169.466ms 50 50 100.00
V2 cmd_read_status spi_device_intercept 36.020s 7.390ms 50 50 100.00
spi_device_flash_all 6.238m 169.466ms 50 50 100.00
V2 cmd_read_jedec spi_device_intercept 36.020s 7.390ms 50 50 100.00
spi_device_flash_all 6.238m 169.466ms 50 50 100.00
V2 cmd_read_sfdp spi_device_intercept 36.020s 7.390ms 50 50 100.00
spi_device_flash_all 6.238m 169.466ms 50 50 100.00
V2 cmd_fast_read spi_device_intercept 36.020s 7.390ms 50 50 100.00
spi_device_flash_all 6.238m 169.466ms 50 50 100.00
V2 cmd_read_pipeline spi_device_intercept 36.020s 7.390ms 50 50 100.00
spi_device_flash_all 6.238m 169.466ms 50 50 100.00
V2 flash_cmd_upload spi_device_upload 29.600s 16.792ms 50 50 100.00
V2 mailbox_command spi_device_mailbox 2.057m 43.655ms 50 50 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 2.057m 43.655ms 50 50 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 2.057m 43.655ms 50 50 100.00
V2 cmd_read_buffer spi_device_flash_mode 1.246m 10.427ms 50 50 100.00
spi_device_read_buffer_direct 16.270s 6.065ms 50 50 100.00
V2 cmd_dummy_cycle spi_device_mailbox 2.057m 43.655ms 50 50 100.00
spi_device_flash_all 6.238m 169.466ms 50 50 100.00
V2 quad_spi spi_device_flash_all 6.238m 169.466ms 50 50 100.00
V2 dual_spi spi_device_flash_all 6.238m 169.466ms 50 50 100.00
V2 4b_3b_feature spi_device_cfg_cmd 39.590s 18.617ms 50 50 100.00
V2 write_enable_disable spi_device_cfg_cmd 39.590s 18.617ms 50 50 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 8.933m 146.251ms 50 50 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 7.351m 93.494ms 50 50 100.00
V2 stress_all spi_device_stress_all 9.905m 364.895ms 50 50 100.00
V2 alert_test spi_device_alert_test 1.160s 68.885us 50 50 100.00
V2 intr_test spi_device_intr_test 1.250s 61.555us 50 50 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 5.710s 946.524us 20 20 100.00
V2 tl_d_illegal_access spi_device_tl_errors 5.710s 946.524us 20 20 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.880s 43.394us 5 5 100.00
spi_device_csr_rw 2.980s 596.724us 20 20 100.00
spi_device_csr_aliasing 18.500s 3.775ms 5 5 100.00
spi_device_same_csr_outstanding 4.970s 163.270us 20 20 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.880s 43.394us 5 5 100.00
spi_device_csr_rw 2.980s 596.724us 20 20 100.00
spi_device_csr_aliasing 18.500s 3.775ms 5 5 100.00
spi_device_same_csr_outstanding 4.970s 163.270us 20 20 100.00
V2 TOTAL 961 961 100.00
V2S tl_intg_err spi_device_sec_cm 1.610s 152.740us 5 5 100.00
spi_device_tl_intg_err 17.930s 3.915ms 20 20 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 17.930s 3.915ms 20 20 100.00
V2S TOTAL 25 25 100.00
Unmapped tests spi_device_flash_mode_ignore_cmds 7.000m 573.391ms 50 50 100.00
TOTAL 1151 1151 100.00