SPI_HOST Simulation Results

Sunday November 02 2025 00:09:31 UTC

GitHub Revision: 0136fdb

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.683m	8.819ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	30.613us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	30.764us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	443.182us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	23.263us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	145.642us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	30.764us	20	20	100.00
		spi_host_csr_aliasing	2.000s	23.263us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	42.920us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	175.792us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	3.000s	180.334us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	39.000s	1.572ms	50	50	100.00
		spi_host_error_cmd	2.000s	16.518us	50	50	100.00
		spi_host_event	5.817m	32.313ms	50	50	100.00
V2	clock_rate	spi_host_speed	20.000s	1.152ms	50	50	100.00
V2	speed	spi_host_speed	20.000s	1.152ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	20.000s	1.152ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	4.083m	14.126ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	62.780us	50	50	100.00
V2	cpol_cpha	spi_host_speed	20.000s	1.152ms	50	50	100.00
V2	full_cycle	spi_host_speed	20.000s	1.152ms	50	50	100.00
V2	duplex	spi_host_smoke	1.683m	8.819ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	1.683m	8.819ms	50	50	100.00
V2	stress_all	spi_host_stress_all	14.733m	1.000s	49	50	98.00
V2	spien	spi_host_spien	4.183m	12.346ms	48	50	96.00
V2	stall	spi_host_status_stall	17.617m	122.040ms	49	50	98.00
V2	Idlecsbactive	spi_host_idlecsbactive	40.000s	3.082ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	39.000s	1.572ms	50	50	100.00
V2	alert_test	spi_host_alert_test	2.000s	24.726us	50	50	100.00
V2	intr_test	spi_host_intr_test	7.000s	44.572us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	550.741us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	550.741us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	30.613us	5	5	100.00
		spi_host_csr_rw	2.000s	30.764us	20	20	100.00
		spi_host_csr_aliasing	2.000s	23.263us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	51.931us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	30.613us	5	5	100.00
		spi_host_csr_rw	2.000s	30.764us	20	20	100.00
		spi_host_csr_aliasing	2.000s	23.263us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	51.931us	20	20	100.00
V2		TOTAL			686	690	99.42
V2S	tl_intg_err	spi_host_tl_intg_err	3.000s	96.586us	20	20	100.00
		spi_host_sec_cm	2.000s	40.742us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	3.000s	96.586us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	7.417m	61.270ms	10	10	100.00
		TOTAL			836	840	99.52

Failure Buckets

• UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 1 failures:

  • Test spi_host_spien has 1 failures.

    • 1.spi_host_spien.7726905908046914119552940464504325758589766456727354795247192555633134291172
      Line 301, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_spien/latest/run.log

        UVM_FATAL @ 10117704147 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0x44c1c814, Comparison=CompareOpEq, exp_data=0x0, call_count=45
        UVM_INFO @ 10117704147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (spi_host_scoreboard.sv:179) scoreboard [scoreboard] Since CSB become active, There's been * half SCKs VS (configopts.csnlead+1)=* has 1 failures:

  • Test spi_host_spien has 1 failures.

    • 22.spi_host_spien.44515704964544357633473387126128360780122976679256748487035230637445553181135
      Line 348, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/22.spi_host_spien/latest/run.log

        UVM_FATAL @ 572159475 ps: (spi_host_scoreboard.sv:179) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Since CSB become active, There's been 2 half SCKs VS (configopts.csnlead+1)=1
        UVM_INFO @ 572159475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 23.spi_host_status_stall.32856842947953505032322875958102666461700098404114616176819209311976565720885
      Line 4220, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/23.spi_host_status_stall/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 15806327471 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
        UVM_ERROR @ 15806327471 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time=15806327000 ps
        UVM_INFO @ 15806327471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test spi_host_stress_all has 1 failures.

    • 37.spi_host_stress_all.64207457665640532567076421073805508746670680163129461696036434096145664821009
      Line 277, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/37.spi_host_stress_all/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---