SRAM_CTRL/MAIN Simulation Results

Sunday November 02 2025 00:09:31 UTC

GitHub Revision: 0136fdb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.905m	5.226ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.040s	15.184us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.060s	20.765us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.640s	176.134us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.100s	13.094us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	6.310s	1.413ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.060s	20.765us	20	20	100.00
		sram_ctrl_csr_aliasing	1.100s	13.094us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.143m	20.917ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.349m	34.008ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	25.171m	12.117ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	5.970m	117.702ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	42.854m	718.635ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	22.687m	22.743ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.343m	71.653ms	50	50	100.00
V2	executable	sram_ctrl_executable	20.387m	30.091ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.601m	528.927us	50	50	100.00
		sram_ctrl_partial_access_b2b	7.867m	100.996ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.614m	2.946ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.720m	7.107ms	50	50	100.00
		sram_ctrl_throughput_w_readback	2.141m	3.663ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	24.778m	43.044ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.250s	2.789ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.483h	1.766s	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.080s	17.260us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.100s	726.384us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.100s	726.384us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.040s	15.184us	5	5	100.00
		sram_ctrl_csr_rw	1.060s	20.765us	20	20	100.00
		sram_ctrl_csr_aliasing	1.100s	13.094us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.220s	231.719us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.040s	15.184us	5	5	100.00
		sram_ctrl_csr_rw	1.060s	20.765us	20	20	100.00
		sram_ctrl_csr_aliasing	1.100s	13.094us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.220s	231.719us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	58.910s	14.702ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.020s	7.141us	0	5	0.00
		sram_ctrl_tl_intg_err	3.320s	269.315us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.020s	7.141us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.320s	269.315us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	24.778m	43.044ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	24.778m	43.044ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.060s	20.765us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	20.387m	30.091ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	20.387m	30.091ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	20.387m	30.091ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.343m	71.653ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	12.740s	11.095ms	46	50	92.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	58.910s	14.702ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	11.280s	5.997ms	38	50	76.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.905m	5.226ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.905m	5.226ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	20.387m	30.091ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.020s	7.141us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.343m	71.653ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.020s	7.141us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.020s	7.141us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.905m	5.226ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.020s	7.141us	0	5	0.00
V2S		TOTAL			124	145	85.52
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.793m	1.907ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1169	1190	98.24

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 12 failures:

  • Test sram_ctrl_readback_err has 12 failures.

    • 3.sram_ctrl_readback_err.3527953736971647270115334488058476168515699592016470078644467975130203249351
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 1346512647 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x56) != exp (0x2d)
        UVM_INFO @ 1346512647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.sram_ctrl_readback_err.81080537356105562681852768401231138356555918990201816641299241320081996069862
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 659223687 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x10) != exp (0x57)
        UVM_INFO @ 659223687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 10 more failures.

• Offending 'reqfifo_rvalid' has 4 failures:

  • Test sram_ctrl_mubi_enc_err has 4 failures.

    • 11.sram_ctrl_mubi_enc_err.87288845911399427627350418655285857636844813956931960837341286481688949187616
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/11.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 2629453236 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 2629453236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 12.sram_ctrl_mubi_enc_err.6946810325998083720410392726944525911973587185951179505435929773322447958532
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/12.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 2865188808 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 2865188808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• Offending '(!$isunknown(rdata_o))' has 2 failures:

  • Test sram_ctrl_sec_cm has 2 failures.

    • 0.sram_ctrl_sec_cm.52514397344757366887953519066128391441876434626581442724000644547826115458047
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   3526699 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   3526699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_sec_cm.9885532254796656005628212587287484999456280711636140547989524409108178172101
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   4907939 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   4907939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 2 failures:

  • Test sram_ctrl_sec_cm has 2 failures.

    • 1.sram_ctrl_sec_cm.37370038804639452979402151304454108284679587877191073837387180806011032613459
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  11668213 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  11668213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.sram_ctrl_sec_cm.34849661418245822702192684931394793520346226413035218008265325364853767823127
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3554843 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3554843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 4.sram_ctrl_sec_cm.73322177239486867726068618758584029794609190634108336153008067861531753959821
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 4328088ps failed at 4328088ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 4369755ps failed at 4369755ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'