SRAM_CTRL/RET Simulation Results

Sunday November 02 2025 00:09:31 UTC

GitHub Revision: 0136fdb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.468m	586.603us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.990s	19.029us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.080s	40.651us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.660s	691.027us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.080s	59.084us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.550s	41.621us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.080s	40.651us	20	20	100.00
		sram_ctrl_csr_aliasing	1.080s	59.084us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	13.040s	1.823ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	7.200s	202.072us	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	28.437m	115.399ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.391m	7.740ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.670m	47.446ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	23.249m	20.080ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	12.580s	4.877ms	50	50	100.00
V2	executable	sram_ctrl_executable	24.223m	107.019ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.626m	785.194us	50	50	100.00
		sram_ctrl_partial_access_b2b	9.203m	154.267ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.645m	516.411us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.671m	598.236us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.844m	1.125ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	21.094m	8.482ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.270s	42.635us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.662h	208.705ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.080s	96.281us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.350s	613.501us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.350s	613.501us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.990s	19.029us	5	5	100.00
		sram_ctrl_csr_rw	1.080s	40.651us	20	20	100.00
		sram_ctrl_csr_aliasing	1.080s	59.084us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.140s	181.562us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.990s	19.029us	5	5	100.00
		sram_ctrl_csr_rw	1.080s	40.651us	20	20	100.00
		sram_ctrl_csr_aliasing	1.080s	59.084us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.140s	181.562us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	5.100s	1.847ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.240s	15.482us	0	5	0.00
		sram_ctrl_tl_intg_err	3.390s	3.344ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.240s	15.482us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.390s	3.344ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	21.094m	8.482ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	21.094m	8.482ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.080s	40.651us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	24.223m	107.019ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	24.223m	107.019ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	24.223m	107.019ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	12.580s	4.877ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.620s	47.705us	41	50	82.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	5.100s	1.847ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.520s	51.841us	39	50	78.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.468m	586.603us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.468m	586.603us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	24.223m	107.019ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.240s	15.482us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	12.580s	4.877ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.240s	15.482us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.240s	15.482us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.468m	586.603us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.240s	15.482us	0	5	0.00
V2S		TOTAL			120	145	82.76
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	8.739m	2.835ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1163	1190	97.73

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 11 failures:

  • Test sram_ctrl_readback_err has 11 failures.

    • 0.sram_ctrl_readback_err.25390828992461597206210387349574798316706840172186987175913508959335645836390
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  55203740 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2f) != exp (0x42)
        UVM_INFO @  55203740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.sram_ctrl_readback_err.114056376803070810512769815290492878814544888074410158006215297072802495189253
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 128346740 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6a) != exp (0x3e)
        UVM_INFO @ 128346740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 9 more failures.

• Offending 'reqfifo_rvalid' has 9 failures:

  • Test sram_ctrl_mubi_enc_err has 9 failures.

    • 1.sram_ctrl_mubi_enc_err.112233295564655915039363215937625376253962417711259195014472998776365922702590
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  30269499 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  30269499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_mubi_enc_err.28227049282386124827792903114054951061879558650326671886437839504659382253633
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  24771895 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  24771895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 7 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 4 failures:

  • Test sram_ctrl_sec_cm has 4 failures.

    • 0.sram_ctrl_sec_cm.109356113007727896328694880889416658142701684180209352600910922695598310509294
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  49980259 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  49980259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.sram_ctrl_sec_cm.13775378033955533785361322225655742788020460276209536637657339459055073873956
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  15481640 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  15481640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 2.sram_ctrl_sec_cm.100179613122804448243842377829563642570147952202716557482398176231700361423907
      Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @  17045679 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  17045679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 7.sram_ctrl_csr_mem_rw_with_rand_reset.4551117010809912260530957276264477530598230040248630498839541557979570801390
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  97398521 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (10 [0xa] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
        UVM_INFO @  97398521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 1 failures.

    • 27.sram_ctrl_stress_all_with_rand_reset.49701797888534012877008783366645157109584086807036420376790034506752275378474
      Line 140, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1274142317 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1274142317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---