0136fdb| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sysrst_ctrl_smoke | 9.470s | 2.112ms | 50 | 50 | 100.00 |
| V1 | input_output_inverted | sysrst_ctrl_in_out_inverted | 10.900s | 2.456ms | 50 | 50 | 100.00 |
| V1 | combo_detect_ec_rst | sysrst_ctrl_combo_detect_ec_rst | 4.010s | 2.442ms | 5 | 5 | 100.00 |
| V1 | combo_detect_ec_rst_with_pre_cond | sysrst_ctrl_combo_detect_ec_rst_with_pre_cond | 10.920s | 2.514ms | 5 | 5 | 100.00 |
| V1 | csr_hw_reset | sysrst_ctrl_csr_hw_reset | 8.500s | 4.034ms | 5 | 5 | 100.00 |
| V1 | csr_rw | sysrst_ctrl_csr_rw | 8.160s | 2.059ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | sysrst_ctrl_csr_bit_bash | 5.478m | 75.970ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sysrst_ctrl_csr_aliasing | 11.890s | 3.185ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sysrst_ctrl_csr_mem_rw_with_rand_reset | 9.240s | 2.080ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sysrst_ctrl_csr_rw | 8.160s | 2.059ms | 20 | 20 | 100.00 |
| sysrst_ctrl_csr_aliasing | 11.890s | 3.185ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 165 | 165 | 100.00 | |||
| V2 | combo_detect | sysrst_ctrl_combo_detect | 7.695m | 168.692ms | 50 | 50 | 100.00 |
| V2 | combo_detect_with_pre_cond | sysrst_ctrl_combo_detect_with_pre_cond | 7.045m | 205.957ms | 96 | 100 | 96.00 |
| V2 | auto_block_key_outputs | sysrst_ctrl_auto_blk_key_output | 10.646m | 316.852ms | 50 | 50 | 100.00 |
| V2 | keyboard_input_triggered_interrupt | sysrst_ctrl_edge_detect | 3.181m | 162.211ms | 49 | 50 | 98.00 |
| V2 | pin_output_keyboard_inversion_control | sysrst_ctrl_pin_override_test | 10.390s | 2.511ms | 50 | 50 | 100.00 |
| V2 | pin_input_value_accessibility | sysrst_ctrl_pin_access_test | 9.070s | 2.210ms | 50 | 50 | 100.00 |
| V2 | ec_power_on_reset | sysrst_ctrl_ec_pwr_on_rst | 19.273m | 558.169ms | 49 | 50 | 98.00 |
| V2 | flash_write_protect_output | sysrst_ctrl_flash_wr_prot_out | 11.390s | 2.613ms | 50 | 50 | 100.00 |
| V2 | ultra_low_power_test | sysrst_ctrl_ultra_low_pwr | 14.971m | 3.793s | 43 | 50 | 86.00 |
| V2 | sysrst_ctrl_feature_disable | sysrst_ctrl_feature_disable | 1.908m | 41.472ms | 2 | 2 | 100.00 |
| V2 | stress_all | sysrst_ctrl_stress_all | 9.710m | 234.975ms | 48 | 50 | 96.00 |
| V2 | alert_test | sysrst_ctrl_alert_test | 8.920s | 2.015ms | 50 | 50 | 100.00 |
| V2 | intr_test | sysrst_ctrl_intr_test | 8.080s | 2.013ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | sysrst_ctrl_tl_errors | 9.540s | 2.041ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sysrst_ctrl_tl_errors | 9.540s | 2.041ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sysrst_ctrl_csr_hw_reset | 8.500s | 4.034ms | 5 | 5 | 100.00 |
| sysrst_ctrl_csr_rw | 8.160s | 2.059ms | 20 | 20 | 100.00 | ||
| sysrst_ctrl_csr_aliasing | 11.890s | 3.185ms | 5 | 5 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 40.990s | 10.630ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | sysrst_ctrl_csr_hw_reset | 8.500s | 4.034ms | 5 | 5 | 100.00 |
| sysrst_ctrl_csr_rw | 8.160s | 2.059ms | 20 | 20 | 100.00 | ||
| sysrst_ctrl_csr_aliasing | 11.890s | 3.185ms | 5 | 5 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 40.990s | 10.630ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 677 | 692 | 97.83 | |||
| V2S | tl_intg_err | sysrst_ctrl_sec_cm | 1.569m | 42.015ms | 5 | 5 | 100.00 |
| sysrst_ctrl_tl_intg_err | 1.988m | 42.393ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sysrst_ctrl_tl_intg_err | 1.988m | 42.393ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | sysrst_ctrl_stress_all_with_rand_reset | 19.120s | 279.845ms | 49 | 50 | 98.00 |
| V3 | TOTAL | 49 | 50 | 98.00 | |||
| TOTAL | 916 | 932 | 98.28 |
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 8 failures:
Test sysrst_ctrl_stress_all has 2 failures.
1.sysrst_ctrl_stress_all.2884663717997313916436625706558399108554527139262359953784740355164689314577
Line 386, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all/latest/run.log
UVM_ERROR @ 10242132324 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 10242382323 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 10242382323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
46.sysrst_ctrl_stress_all.35793690695493425814536173689780448779577173736611434388463591045495110628781
Line 382, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_stress_all/latest/run.log
UVM_ERROR @ 181129492581 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 181129512988 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 181129512988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sysrst_ctrl_ultra_low_pwr has 5 failures.
5.sysrst_ctrl_ultra_low_pwr.871176091179328517920272300587649645924211619514575084721272798613300352424
Line 381, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 4127201626 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 4127223847 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 4127223847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.sysrst_ctrl_ultra_low_pwr.18433401840006314225264263225088902888831783015683008640688999436890835798746
Line 381, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 7430179319 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 7430262652 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 7430262652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test sysrst_ctrl_edge_detect has 1 failures.
24.sysrst_ctrl_edge_detect.3971700086178011101095094426010395367754445532175148924765833214207783717263
Line 385, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_edge_detect/latest/run.log
UVM_ERROR @ 2813234725 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 2813274724 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 2813274724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 2 failures:
46.sysrst_ctrl_ultra_low_pwr.52672138377033691655426932747929974546117483897397085710581524470237802041387
Line 382, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 1118971092593 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 1119133592593 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
UVM_INFO @ 1788508592593 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 1788522362628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.sysrst_ctrl_ultra_low_pwr.109532801943894550489510223371290958914458215101718707179217848855096968517187
Line 381, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 2242214370 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_ERROR @ 3939714370 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 3939714370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:261) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] time out waiting for rst_req == * has 1 failures:
13.sysrst_ctrl_combo_detect_with_pre_cond.114711409623786852710770315805493516828435400744895965114733374685952024096540
Line 392, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_FATAL @ 15556985824 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:261) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] time out waiting for rst_req == 1
UVM_INFO @ 15556985824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == * has 1 failures:
18.sysrst_ctrl_ec_pwr_on_rst.15047439429317551572453231810848077059717566165304328415816581931991415530661
Line 381, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_ec_pwr_on_rst/latest/run.log
UVM_FATAL @ 2207650349 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
UVM_INFO @ 2207650349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) has 1 failures:
22.sysrst_ctrl_combo_detect_with_pre_cond.82021614749117888195132756802325542832246798514436223540740971640345602107023
Line 394, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 26167101083 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 26167101083 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 26167101083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:109) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (* [*] vs * [*]) has 1 failures:
31.sysrst_ctrl_stress_all_with_rand_reset.110168696281450232663053868676807553973881652353134024797811221356501528487140
Line 409, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6873105603 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (1 [0x1] vs 0 [0x0])
UVM_INFO @ 6876938187 ps: (cip_base_vseq.sv:1166) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
Stress w/ reset is done for run 4/5
UVM_INFO @ 6888912681 ps: (cip_base_vseq.sv:1097) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 5/5
UVM_INFO @ 6888912681 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_tl_errors_vseq 1/388
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 1 failures:
49.sysrst_ctrl_combo_detect_with_pre_cond.108687738592141793784976466551086943163378370388185060551748808100503927804161
Line 409, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 51238771572 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 51238771572 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 51238771572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(2) +/-* has 1 failures:
61.sysrst_ctrl_combo_detect_with_pre_cond.49041580096071891638259147494541014918173021708339149308316083663850466126134
Line 399, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/61.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 15184718306 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(2) +/-4
UVM_ERROR @ 15184718306 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(2) +/-4
UVM_INFO @ 15184718306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---