CHIP Simulation Results

Sunday November 02 2025 00:09:31 UTC

GitHub Revision: `0136fdb`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	3.216m	3.287ms	3	3	100.00
		chip_sw_example_rom	2.192m	2.771ms	3	3	100.00
		chip_sw_example_manufacturer	3.361m	2.782ms	3	3	100.00
		chip_sw_example_concurrency	2.981m	2.659ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	5.027m	6.938ms	4	5	80.00
V1	csr_rw	chip_csr_rw	10.674m	5.968ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	42.340m	31.069ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	1.448h	38.866ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	13.230m	8.616ms	9	20	45.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.448h	38.866ms	5	5	100.00
		chip_csr_rw	10.674m	5.968ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	11.340s	244.111us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.040m	4.484ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.040m	4.484ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.040m	4.484ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	8.871m	4.872ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	8.871m	4.872ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	9.511m	4.085ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	8.935m	4.498ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	8.155m	4.510ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	36.275m	12.912ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	36.950m	12.795ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	16.853m	8.999ms	5	5	100.00
V1		TOTAL			208	220	94.55
V2	chip_pin_mux	chip_padctrl_attributes	3.346m	5.291ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.346m	5.291ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	4.307m	3.780ms	2	3	66.67
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	5.311m	5.799ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	4.151m	3.058ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	25.202m	18.062ms	5	5	100.00
		chip_tap_straps_testunlock0	7.987m	7.326ms	5	5	100.00
		chip_tap_straps_rma	10.673m	8.821ms	5	5	100.00
		chip_tap_straps_prod	14.613m	10.846ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	3.423m	3.237ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	16.713m	8.482ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	9.168m	5.301ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	9.168m	5.301ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.332m	7.834ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	1.179h	25.734ms	0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	8.510m	4.619ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	12.729m	6.189ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.204h	18.262ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	3.608m	3.409ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	16.228m	7.298ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	2.680m	2.637ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	34.269m	12.634ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.839m	3.646ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	7.183m	4.800ms	3	3	100.00
		chip_sw_clkmgr_jitter	3.277m	3.347ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.679m	3.114ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	10.756m	7.008ms	4	5	80.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	5.836m	4.925ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.914m	3.406ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	5.836m	4.925ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	3.023m	2.569ms	3	3	100.00
		chip_sw_aes_smoketest	2.719m	2.970ms	3	3	100.00
		chip_sw_aon_timer_smoketest	4.587m	2.899ms	3	3	100.00
		chip_sw_clkmgr_smoketest	3.276m	3.270ms	3	3	100.00
		chip_sw_csrng_smoketest	3.345m	2.718ms	3	3	100.00
		chip_sw_entropy_src_smoketest	21.695m	8.372ms	3	3	100.00
		chip_sw_gpio_smoketest	4.427m	3.249ms	3	3	100.00
		chip_sw_hmac_smoketest	4.681m	4.085ms	3	3	100.00
		chip_sw_kmac_smoketest	4.433m	2.852ms	3	3	100.00
		chip_sw_otbn_smoketest	26.024m	10.149ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	5.006m	5.643ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	6.664m	6.475ms	3	3	100.00
		chip_sw_rv_plic_smoketest	3.449m	2.243ms	3	3	100.00
		chip_sw_rv_timer_smoketest	3.082m	2.760ms	3	3	100.00
		chip_sw_rstmgr_smoketest	3.526m	3.025ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	2.675m	2.149ms	3	3	100.00
		chip_sw_uart_smoketest	3.713m	2.998ms	3	3	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	3.476m	2.721ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	7.965m	5.020ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.326h	60.624ms	3	3	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	1.022h	16.162ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	19.299m	14.085ms	0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.600m	2.964ms	0	3	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	4.589m	3.770ms	0	3	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.876h	53.256ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.032h	56.817ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	5.996m	4.080ms	1	30	3.33
V2	tl_d_illegal_access	chip_tl_errors	5.996m	4.080ms	1	30	3.33
V2	tl_d_outstanding_access	chip_csr_aliasing	1.448h	38.866ms	5	5	100.00
		chip_same_csr_outstanding	1.129h	32.670ms	20	20	100.00
		chip_csr_hw_reset	5.027m	6.938ms	4	5	80.00
		chip_csr_rw	10.674m	5.968ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.448h	38.866ms	5	5	100.00
		chip_same_csr_outstanding	1.129h	32.670ms	20	20	100.00
		chip_csr_hw_reset	5.027m	6.938ms	4	5	80.00
		chip_csr_rw	10.674m	5.968ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.306m	2.111ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.210s	58.984us	100	100	100.00
		xbar_smoke_large_delays	1.826m	10.048ms	100	100	100.00
		xbar_smoke_slow_rsp	1.577m	6.325ms	100	100	100.00
		xbar_random_zero_delays	48.770s	615.573us	100	100	100.00
		xbar_random_large_delays	8.720m	56.171ms	100	100	100.00
		xbar_random_slow_rsp	8.127m	35.796ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	57.740s	1.383ms	100	100	100.00
		xbar_error_and_unmapped_addr	56.110s	1.521ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.267m	2.441ms	100	100	100.00
		xbar_error_and_unmapped_addr	56.110s	1.521ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.324m	3.335ms	100	100	100.00
		xbar_access_same_device_slow_rsp	16.066m	79.776ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.403m	2.710ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	7.368m	15.545ms	100	100	100.00
		xbar_stress_all_with_error	8.883m	18.381ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	14.029m	25.516ms	100	100	100.00
		xbar_stress_all_with_reset_error	13.470m	30.169ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	1.022h	16.162ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	55.587m	25.529ms	2	3	66.67
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	1.036h	22.830ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	45.616m	11.452ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	1.034h	16.375ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	1.028h	17.059ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	1.027h	15.920ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	58.740m	14.922ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	20.050s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	18.650s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	24.190s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	25.000s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	19.630s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	18.130s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	19.630s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	28.690s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	18.740s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	18.700s	10.240us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	29.510s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	18.550s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	30.910s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	20.770s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	17.280s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	18.810s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	22.340s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	19.060s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	20.800s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	23.750s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	18.400s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	25.120s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	18.310s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	21.580s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	18.880s	10.280us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	47.354m	11.739ms	3	3	100.00
		rom_e2e_asm_init_dev	1.083h	19.204ms	3	3	100.00
		rom_e2e_asm_init_prod	1.083h	16.784ms	3	3	100.00
		rom_e2e_asm_init_prod_end	1.038h	16.039ms	3	3	100.00
		rom_e2e_asm_init_rma	58.120m	15.162ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	1.010h	15.199ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	1.025h	15.291ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	1.015h	14.585ms	3	3	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	1.073h	16.969ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup			0	3	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup			0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.688m	3.036ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	3.608m	3.409ms	3	3	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.887m	2.678ms	3	3	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.031m	3.217ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	30.619m	11.239ms	3	3	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	4.244m	2.997ms	0	3	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	7.748m	5.068ms	3	3	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	10.862m	5.840ms	99	100	99.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	12.661m	5.814ms	3	3	100.00
		chip_plic_all_irqs_10	5.391m	3.838ms	3	3	100.00
		chip_plic_all_irqs_20	9.869m	4.352ms	3	3	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	4.300m	3.387ms	2	3	66.67
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	23.057m	10.776ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	4.663m	3.267ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	4.184m	2.943ms	0	90	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings			0	3	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	21.002m	8.058ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	19.798m	7.426ms	3	3	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	17.229m	8.101ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.180h	254.986ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.683m	3.664ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	5.006m	5.643ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.683m	3.664ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	9.565m	8.241ms	1	3	33.33
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	9.565m	8.241ms	1	3	33.33
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.292m	6.159ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	8.150m	4.905ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	13.741m	6.465ms	3	3	100.00
		chip_sw_aes_idle	4.031m	3.217ms	3	3	100.00
		chip_sw_hmac_enc_idle	3.744m	2.927ms	3	3	100.00
		chip_sw_kmac_idle	2.796m	2.314ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	6.129m	3.902ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	6.770m	4.493ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	5.185m	3.849ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	6.465m	3.731ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	18.690m	9.489ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	8.167m	4.007ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	8.838m	5.424ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	8.475m	4.255ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	8.258m	4.220ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	8.319m	3.908ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	9.339m	4.989ms	3	3	100.00
		chip_sw_ast_clk_outputs	11.332m	7.834ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	9.037m	8.487ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	8.475m	4.255ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	8.258m	4.220ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	8.510m	4.619ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	12.729m	6.189ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.204h	18.262ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	3.608m	3.409ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	16.228m	7.298ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	2.680m	2.637ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	34.269m	12.634ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.839m	3.646ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	7.183m	4.800ms	3	3	100.00
		chip_sw_clkmgr_jitter	3.277m	3.347ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.593m	2.755ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	8.640m	4.363ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	13.129m	7.648ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.273h	24.681ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	3.693m	3.453ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.911m	2.810ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	13.540m	8.171ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	4.078m	3.739ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	7.123m	4.594ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	28.487m	24.738ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	4.074h	130.560ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.332m	7.834ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	8.133m	4.719ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.607m	2.941ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	10.862m	5.840ms	99	100	99.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	21.002m	8.058ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	18.443m	6.773ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	4.295m	3.491ms	0	3	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	10.047m	7.708ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.149m	3.390ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	2.494h	52.152ms	10	10	100.00
		chip_sw_entropy_src_ast_rng_req	3.259m	2.414ms	3	3	100.00
		chip_sw_edn_entropy_reqs	15.020m	7.517ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	3.259m	2.414ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	18.443m	6.773ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	3.063m	2.694ms	3	3	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	31.983m	26.071ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	11.774m	5.738ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	12.729m	6.189ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	7.635m	4.287ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	8.510m	4.619ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.394h	43.238ms	3	3	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	31.983m	26.071ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	5.000m	3.150ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	35.881m	13.342ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.511m	5.035ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.394h	43.238ms	3	3	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.511m	5.035ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.511m	5.035ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	5.511m	5.035ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.511m	5.035ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	10.862m	5.840ms	99	100	99.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	7.644m	14.148ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	12.104m	5.619ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	7.288m	5.212ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	7.288m	5.212ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.876m	2.902ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	2.680m	2.637ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.744m	2.927ms	3	3	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	4.013m	2.481ms	0	3	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	7.953m	3.581ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	9.276m	5.767ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	8.199m	4.680ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	10.653m	5.498ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	6.498m	3.936ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	35.881m	13.342ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	34.269m	12.634ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	21.564m	8.460ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	30.619m	11.239ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	48.599m	13.752ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.360m	3.491ms	3	3	100.00
		chip_sw_kmac_mode_kmac	4.765m	3.604ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.839m	3.646ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	35.881m	13.342ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	16.199m	11.507ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	3.669m	3.466ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	27.523m	8.251ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.796m	2.314ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	7.748m	5.068ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	25.202m	18.062ms	5	5	100.00
		chip_tap_straps_rma	10.673m	8.821ms	5	5	100.00
		chip_tap_straps_prod	14.613m	10.846ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.906m	2.812ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	16.199m	11.507ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	16.199m	11.507ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	16.199m	11.507ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	31.994m	12.197ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	5.511m	5.035ms	3	3	100.00
		chip_sw_flash_rma_unlocked	1.394h	43.238ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	4.828m	3.615ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	12.838m	6.504ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	13.842m	7.899ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	11.307m	6.173ms	0	3	0.00
		chip_sw_lc_ctrl_transition	16.199m	11.507ms	15	15	100.00
		chip_sw_keymgr_key_derivation	35.881m	13.342ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	7.655m	8.090ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	13.505m	8.426ms	3	3	100.00
		chip_prim_tl_access	7.644m	14.148ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	9.037m	8.487ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	8.167m	4.007ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	8.838m	5.424ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	8.475m	4.255ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	8.258m	4.220ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	8.319m	3.908ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	9.339m	4.989ms	3	3	100.00
		chip_tap_straps_dev	25.202m	18.062ms	5	5	100.00
		chip_tap_straps_rma	10.673m	8.821ms	5	5	100.00
		chip_tap_straps_prod	14.613m	10.846ms	5	5	100.00
		chip_rv_dm_lc_disabled	2.469m	4.441ms	0	3	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.475m	3.925ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.244m	3.288ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.074m	3.860ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.761m	3.392ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	36.009m	35.659ms	3	3	100.00
		chip_rv_dm_lc_disabled	2.469m	4.441ms	0	3	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.390h	48.569ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.559h	47.737ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	10.782m	9.165ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.490h	48.011ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	36.009m	35.659ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.648m	2.740ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.620m	2.916ms	3	3	100.00
		rom_volatile_raw_unlock	1.553m	2.380ms	3	3	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	1.161h	16.991ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.204h	18.262ms	3	3	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	13.741m	6.465ms	3	3	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	13.741m	6.465ms	3	3	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	13.741m	6.465ms	3	3	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	6.735m	3.909ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	16.199m	11.507ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	31.983m	26.071ms	3	3	100.00
		chip_sw_otbn_mem_scramble	6.735m	3.909ms	3	3	100.00
		chip_sw_keymgr_key_derivation	35.881m	13.342ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	8.539m	4.967ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.934m	2.973ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	31.983m	26.071ms	3	3	100.00
		chip_sw_otbn_mem_scramble	6.735m	3.909ms	3	3	100.00
		chip_sw_keymgr_key_derivation	35.881m	13.342ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	8.539m	4.967ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.934m	2.973ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	16.199m	11.507ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	7.951m	5.153ms	3	3	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.906m	2.812ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	4.828m	3.615ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	12.838m	6.504ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	13.842m	7.899ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	11.307m	6.173ms	0	3	0.00
		chip_sw_lc_ctrl_transition	16.199m	11.507ms	15	15	100.00
		chip_prim_tl_access	7.644m	14.148ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	7.644m	14.148ms	3	3	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	19.357m	8.947ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	7.050m	7.606ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	24.310m	24.461ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	5.885m	7.074ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	6.485m	7.021ms	0	3	0.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	9.691m	7.560ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	26.611m	24.405ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	17.112m	12.661ms	2	3	66.67
		chip_sw_aon_timer_wdog_bite_reset	9.565m	8.241ms	1	3	33.33
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	17.517m	13.051ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	6.287m	4.270ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	7.050m	7.606ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	6.666m	4.191ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	28.626m	23.137ms	0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	8.310m	7.944ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	7.925m	5.977ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	12.508m	12.538ms	0	3	0.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	15.786m	8.672ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	21.164m	10.332ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	32.228m	23.643ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	4.167m	2.946ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	10.862m	5.840ms	99	100	99.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	7.655m	8.090ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	7.655m	8.090ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	21.164m	10.332ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	12.508m	12.538ms	0	3	0.00
		chip_sw_pwrmgr_wdog_reset	6.287m	4.270ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	5.006m	5.643ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	5.874m	4.827ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	6.087m	3.315ms	0	3	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	5.443m	4.309ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	23.057m	10.776ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.264m	3.094ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	10.862m	5.840ms	99	100	99.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	19.798m	7.426ms	3	3	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	9.778m	4.856ms	3	3	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	10.869m	4.865ms	3	3	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.763m	2.454ms	3	3	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.934m	2.973ms	3	3	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	6.087m	3.315ms	0	3	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	6.087m	3.315ms	0	3	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	19.169m	12.470ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	18.150m	13.210ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	5.874m	4.827ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	7.771m	5.194ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	7.082m	7.408ms	3	3	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	10.673m	8.821ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	2.469m	4.441ms	0	3	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	12.661m	5.814ms	3	3	100.00
		chip_plic_all_irqs_10	5.391m	3.838ms	3	3	100.00
		chip_plic_all_irqs_20	9.869m	4.352ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.045m	2.763ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	3.449m	2.878ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	1.022h	16.162ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	10.600m	7.022ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.925m	3.449ms	0	3	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	4.040m	3.361ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	4.192m	3.088ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.539m	4.967ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	7.183m	4.800ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	8.125m	6.840ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	10.422m	7.804ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	13.505m	8.426ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	10.862m	5.840ms	99	100	99.00
		chip_sw_data_integrity_escalation	9.168m	5.301ms	6	6	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	15.786m	8.672ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	24.197m	23.405ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.872m	2.912ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	5.631m	3.606ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	7.684m	4.824ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	24.197m	23.405ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	24.197m	23.405ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	54.540m	20.807ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	54.540m	20.807ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	6.268m	6.683ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup			0	3	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.750m	2.806ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.190m	2.421ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	3.724m	3.332ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	6.693m	3.776ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	19.127m	8.274ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.911h	31.075ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	38.181m	12.756ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	3.302m	2.784ms	1	1	100.00
V2		TOTAL			2457	2657	92.47
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	3.961m	3.092ms	3	3	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.390m	2.544ms	2	3	66.67
V2S		TOTAL			5	6	83.33
V3	chip_sw_coremark	chip_sw_coremark	4.163h	72.493ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	21.127m	6.683ms	3	3	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	4.319m	3.613ms	0	1	0.00
		rom_e2e_jtag_debug_dev	11.549m	14.160ms	0	1	0.00
		rom_e2e_jtag_debug_rma	23.872m	11.053ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	3.947m	4.052ms	1	1	100.00
		rom_e2e_jtag_inject_dev	4.184m	4.093ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.444m	4.582ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	14.385s		0	3	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	10.452m	5.206ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	6.909m	2.684ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	26.311m	7.359ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	34.677m	10.814ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	4.582m	2.509ms	3	3	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	12.453m	5.356ms	3	3	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.513m	3.040ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	2.831m	3.027ms	0	1	0.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	7.580m	5.920ms	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	7.359m	5.340ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	21.164m	10.332ms	3	3	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	4.319m	3.613ms	0	1	0.00
		rom_e2e_jtag_debug_dev	11.549m	14.160ms	0	1	0.00
		rom_e2e_jtag_debug_rma	23.872m	11.053ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	7.780m	5.289ms	3	3	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	10.862m	5.840ms	99	100	99.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.977h	37.492ms	1	3	33.33
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.977h	37.492ms	1	3	33.33
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	4.083m	3.909ms	3	3	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	8.871m	4.872ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.051h	18.784ms	1	1	100.00
V3		TOTAL			43	51	84.31
	Unmapped tests	chip_sival_flash_info_access	3.413m	3.082ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	9.109m	5.546ms	3	3	100.00
		chip_sw_otp_ctrl_rot_auth_config	34.849m	22.704ms	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	3.225m	2.682ms	3	3	100.00
		chip_sw_otp_ctrl_descrambling	3.853m	3.302ms	3	3	100.00
		chip_sw_pwrmgr_lowpower_cancel	5.703m	4.138ms	2	3	66.67
		chip_sw_pwrmgr_sleep_wake_5_bug	14.822s		0	3	0.00
		chip_sw_flash_ctrl_write_clear	4.367m	3.160ms	3	3	100.00
		TOTAL			2730	2956	92.35

Failure Buckets

UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 90 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 90 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.20981315531233760715402876271370880936354863229467777837514646219928251958501
    Line 401, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3155.761655 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3155.761655 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_alert_handler_lpg_sleep_mode_alerts.69385069250878540293962566712923630370350395851838963844190974127464865798283
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2566.313945 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2566.313945 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 88 more failures.
Offending '(rstreqs[*] && (reset_cause == HwReq))' has 12 failures:
- Test chip_sw_pwrmgr_random_sleep_all_reset_reqs has 3 failures.
  - 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.914046188157419287781699974352013369248895091433754395761548431001863269101
    Line 423, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 13080.154000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 13080.154000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.73989228914715545877972782975650260591674921724602332438633703697216262451781
    Line 433, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 12537.798000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 12537.798000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_pwrmgr_deep_sleep_por_reset has 3 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_por_reset.99100344648569969080632465502243779909013847071892636531577861196440766863015
    Line 412, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log
```
      Offending '(rstreqs[0] && (reset_cause == HwReq))'
  UVM_ERROR @ 7020.666500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 7020.666500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_pwrmgr_deep_sleep_por_reset.49981609670874804039425615691171627848521560226927750271216388591079884333575
    Line 406, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log
```
      Offending '(rstreqs[0] && (reset_cause == HwReq))'
  UVM_ERROR @ 7235.926000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 7235.926000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_pwrmgr_random_sleep_power_glitch_reset has 3 failures.
  - 0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.79027380028935621645536354740116159053708386602524781584352271933890671322243
    Line 475, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 23136.635000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 23136.635000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.41400097175381067848970305945667759485141608186717808507426305882232783378757
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 5820.032000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 5820.032000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_pwrmgr_deep_sleep_all_reset_reqs has 1 failures.
  - 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.36371477207772499782792357743526683811649992008788190703880083319577914235090
    Line 418, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 9796.876000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 9796.876000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aon_timer_wdog_bite_reset has 2 failures.
  - 1.chip_sw_aon_timer_wdog_bite_reset.41159023203082416100611832784938508475947811284721464913312198882025562800086
    Line 400, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 7580.223000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 7580.223000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.chip_sw_aon_timer_wdog_bite_reset.105547679745885088099227735393423776706735665381538223940025554295502770827708
    Line 400, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 7831.750000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 7831.750000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.39359540029721985639966178866260453955113344018746879991333976919816821631097
    Line 998, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.30019954329016225667153073527666501829560717854125324656125970054609156297757
    Line 609, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.86170158666647107085567866521559599650764166715079295426725562522144017546098
    Line 577, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3921524255313567937385039002941140854301986595288715913148842564800741557027
    Line 599, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.77379257044435083314095979776633179917114318673238012552325928857926223979993
    Line 617, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
Job timed out after * minutes has 8 failures:
- Test chip_sw_rv_timer_systick_test has 2 failures.
  - 0.chip_sw_rv_timer_systick_test.49299053589204431597593342045273642960929063893940103774045083774426184943832
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job timed out after 120 minutes
```
  - 1.chip_sw_rv_timer_systick_test.39477966916625372248188022981152535252918502694149266489973936874337752016712
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job timed out after 120 minutes
```
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 3 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.81251033686175958606950023705250481000210164065937826884226792798975882674160
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  Job timed out after 60 minutes
```
  - 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.27677019829373822315510251232935770219036465698745904910489539600390183095510
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 1 more failures.
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 3 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.74282840855786624998457970134754010512023298286730002247095623675704543570158
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
  - 1.chip_sw_alert_handler_lpg_sleep_mode_pings.36827770720963137727435385391597457153032195252613927291992489951988124584290
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
  - ... and 1 more failures.

Job returned non-zero exit code has 6 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 3 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.46240148542836611926054680865242404006733209823281260721369377603207596293418
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 2.307s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_pwrmgr_sleep_wake_5_bug.23378676351407227066075813723899633915778400863255717307451023519570673794250
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.742s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_self_hash has 3 failures.

0.rom_e2e_self_hash.34042616402477178651062545068725595822371522033978801606529848669087561052857
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 1.007s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_self_hash.11879574426367010990876099326429433619225172411947130144573150185382832723558
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.178s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.84431848015759636985393969519828751341112359305609256796354085896857482299070
    Line 621, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.49187365494767684326670459441090539414467804315477674248942696467436113452287
    Line 614, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.65063457276445022596882076780831810565714210867768255891741955867266274043516
    Line 613, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.12483050762712327354424858554928683947837352036795346963064402662868375151607
    Line 617, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.61776006633246418767442184024630229627213576771075927975516043227672101037155
    Line 640, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 4 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.84112425683208819527374966484289411279291741217353551871115706445556933850435
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 3026.791434 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 3026.791434 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 3 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.57070441738929259178700340843098668433154137810896225699355742231831212303791
    Line 393, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 2880.746960 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 2880.746960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_csrng_fuse_en_sw_app_read_test.77602754905625075719025123989624658459483124780868563800563996685983103835316
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 3491.137114 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 3491.137114 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * has 3 failures:
- Test chip_sw_otp_ctrl_lc_signals_rma has 3 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_rma.65476276379254387270217538706123593797322687178564947299844875176977335006557
    Line 550, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 6465.655040 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
  UVM_INFO @ 6465.655040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_otp_ctrl_lc_signals_rma.11710849534284463400599873380021040528469622424785864522383941760475696109309
    Line 422, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 6172.820126 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
  UVM_INFO @ 6172.820126 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 3 failures:
- Test chip_sw_hmac_oneshot has 3 failures.
  - 0.chip_sw_hmac_oneshot.13044435649173112939259895301809651604251537959148479957218920755064219010931
    Line 408, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 3624.447911 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 3624.447911 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_hmac_oneshot.108157895924364069712645726907457841462428582759590830126927835216864830945196
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 3081.668396 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 3081.668396 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 3 failures:

Test chip_rv_dm_lc_disabled has 3 failures.

0.chip_rv_dm_lc_disabled.51794904185402986120027447803516843502665997234297101504793362172751835721670
Line 198, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log

  UVM_ERROR @ 2788.208000 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x10564 read out mismatch
  UVM_INFO @ 2788.208000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_rv_dm_lc_disabled.80435735452876535243886092539550563244659016718769232813685155454956219983103
Line 208, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_rv_dm_lc_disabled/latest/run.log

  UVM_ERROR @ 4437.505386 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x105a0 read out mismatch
  UVM_INFO @ 4437.505386 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 3 failures:

Test chip_sw_power_idle_load has 3 failures.

0.chip_sw_power_idle_load.5110716087495431965701887156230316283643312995793666946986588343801399129935
Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log

  UVM_ERROR @ 2961.870000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2961.870000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_power_idle_load.112622847132273100187029748770314785925119774055608377124473578577659747355700
Line 399, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_idle_load/latest/run.log

  UVM_ERROR @ 2963.597000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2963.597000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 3 failures:

Test chip_sw_power_sleep_load has 3 failures.

0.chip_sw_power_sleep_load.93594627355426866035041363665964759705926154272583711550394047173418923546414
Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log

  UVM_ERROR @ 3769.923000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3769.923000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_power_sleep_load.9420106564529914050320363405128564892862836660319770502533713473816836379680
Line 396, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_sleep_load/latest/run.log

  UVM_ERROR @ 2854.535000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2854.535000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 3 failures:
- Test chip_sw_ast_clk_rst_inputs has 3 failures.
  - 0.chip_sw_ast_clk_rst_inputs.47515018895727513441304657666308089559984123373801878451070955786650439409193
    Line 415, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 25734.342881 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 25734.342881 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_ast_clk_rst_inputs.10914741856449152789915157699112211597626298844111775280098999136391837330260
    Line 412, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 19813.478576 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 19813.478576 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.37881510779976970544310582725784228448076603152863102982999341037091379908636
    Line 566, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.70201830758851711211001358903658045719428771401943299725930561847990069245763
    Line 724, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.109227104648606718338522967383329942064454501620130108627264777250386923514540
    Line 571, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_lc_raw_unlock_vseq.sv:57) [chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement has 3 failures:
- Test rom_raw_unlock has 3 failures.
  - 0.rom_raw_unlock.13433284360044192804135167219716046072487638519685279990057283587055370917782
    Line 460, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log
```
  UVM_FATAL @ 16023.419305 us: (chip_sw_lc_raw_unlock_vseq.sv:57) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement
  UVM_INFO @ 16023.419305 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rom_raw_unlock.70086249782027382647981810348951740401291373508770138571218928937168919503770
    Line 422, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log
```
  UVM_FATAL @ 14085.173500 us: (chip_sw_lc_raw_unlock_vseq.sv:57) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement
  UVM_INFO @ 14085.173500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 2 failures:
- Test chip_sw_alert_test has 2 failures.
  - 0.chip_sw_alert_test.108543738450244302827879944821576685683995849280053878489021316944659698451450
    Line 389, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2997.379449 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2997.379449 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.chip_sw_alert_test.44516136525178426354194745302631842032552327644689344891027519177457611084520
    Line 389, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3233.814125 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 43!
  UVM_INFO @ 3233.814125 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:905) virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault has 2 failures:
- Test chip_sw_alert_handler_entropy has 1 failures.
  - 0.chip_sw_alert_handler_entropy.78700389116859210218419930184131348945848886692330460787338535054730967226708
    Line 519, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_entropy/latest/run.log
```
  UVM_ERROR @ 3386.762544 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
  UVM_INFO @ 3386.762544 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_all_escalation_resets has 1 failures.
  - 19.chip_sw_all_escalation_resets.103743928975616073235199975782965133990017820847258492601655674441412374420341
    Line 401, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/19.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2479.719892 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
  UVM_INFO @ 2479.719892 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending '(pend_req[h2d.a_source].pend == *)' has 2 failures:

Test rom_e2e_shutdown_output has 1 failures.

0.rom_e2e_shutdown_output.71655977137643506044633986831176302940387300870040988931005975776478338378256
Line 461, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log

      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_rstmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 4988458868ps failed at 4988458868ps
      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_rstmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 4988755972ps failed at 4988755972ps
      Offending '(pend_req[h2d.a_source].pend == 0)'

Test rom_e2e_jtag_debug_dev has 1 failures.

0.rom_e2e_jtag_debug_dev.42161968496035972932599545246555983931431954980127362994318328750746133629907
Line 514, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log

      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_rstmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 4165492593ps failed at 4165492593ps
      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_rstmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 4165670625ps failed at 4165670625ps
      Offending '(pend_req[h2d.a_source].pend == 0)'

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.73968217689902748371624648164478813403662435262391820309006763914020175673421
    Line 692, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.30727218546309416934134136022498592217589392319790816624382291906333677452437
    Line 705, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.15010989956627688423124522115282905087075647724729805948878974284758626264325
    Line 714, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.5683395277422608943133958202790615197569980687239343635318678760718193243792
    Line 542, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 2 failures:
- Test chip_sw_spi_device_pass_through_collision has 2 failures.
  - 1.chip_sw_spi_device_pass_through_collision.112232473771544520174440315620485022655613260216191642966401305429523507173091
    Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2767.524256 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2767.524256 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.chip_sw_spi_device_pass_through_collision.82244906172195547210715358175692666016101323467043180951515824720672649918052
    Line 407, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3449.037433 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3449.037433 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.24445165955406420315468114271544993300466838816995851805560471218804284210812
    Line 534, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2748.963556 us: (chip_sw_spi_passthrough_collision_vseq.sv:183) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_spi_passthrough_collision_vseq] Compare mismatch
  host_rsp:
  -------------------------------------------------------------------------
  Name                               Type              Size  Value
  -------------------------------------------------------------------------
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.112161469052419054508351514670710176769902804889922537539230372985560388250465
    Line 437, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 22704.135300 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 22704.135300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@109790) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.27736635117707921246495676655725377691211929887079636938025075741121829484566
Line 415, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3315.315112 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@109790) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3315.315112 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35766) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.10024216968661831777287655055882147035913187223894341223648101218421529587438
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2507.236184 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35766) { a_addr: 'h104cc  a_data: 'hff4f136c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h16  a_opcode: 'h4  a_user: 'h195d1  d_param: 'h0  d_source: 'h16  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2507.236184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() has 1 failures:
- Test chip_sw_pwrmgr_lowpower_cancel has 1 failures.
  - 0.chip_sw_pwrmgr_lowpower_cancel.81851602775365877176082301814711361743046466674904846875727661369939838663032
    Line 411, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_lowpower_cancel/latest/run.log
```
  UVM_ERROR @ 3319.207516 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
  UVM_INFO @ 3319.207516 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.9435844597316638675919994723332898677659016390208236109740735446207481681750
    Line 616, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2555413028579513787437565561958051541749229597489288604584969695805344588908
    Line 671, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds has 1 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.54306058731591435736032546103160568208016422711857231670580575565474803299482
    Line 542, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_ERROR @ 3613.428391 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
  UVM_INFO @ 3613.428391 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 1 failures.
  - 1.chip_sw_sleep_pin_mio_dio_val.109958801914272792488693666990451061782706945482204033127353989584746720909657
    Line 526, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 3779.791500 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 3779.791500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@81974) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

1.chip_sw_rstmgr_cpu_info.70789899067334456392846312476803575694920037514687347731830799446711948445134
Line 419, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3433.050010 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@81974) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3433.050010 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 1.chip_sw_alert_test.72663886023772520928699325546775700684771116379784072731784618495636478207147
    Line 389, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2805.788292 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert 28!
  UVM_INFO @ 2805.788292 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38220) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

1.chip_tl_errors.113887477855489753463751352949590481590400547534452410979465407366188011338123
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2314.238752 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38220) { a_addr: 'h10498  a_data: 'h8b5ad3dc  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3f  a_opcode: 'h4  a_user: 'h19554  d_param: 'h0  d_source: 'h3f  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2314.238752 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32348) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

1.chip_csr_mem_rw_with_rand_reset.10551450712073071785333930538331047784576784206232847771503152932883924592111
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 1901.975845 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32348) { a_addr: 'h10524  a_data: 'hdb5b699  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h15  a_opcode: 'h4  a_user: 'h186e9  d_param: 'h0  d_source: 'h15  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1901.975845 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@78478) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

2.chip_sw_rstmgr_cpu_info.113509516769563430012805291219072056915622991666465846152210892682658884016108
Line 414, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 2959.527945 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@78478) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2959.527945 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33686) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

2.chip_tl_errors.49100912699844135726229503995994178361625153724054605287068691083067408874446
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2176.688894 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33686) { a_addr: 'h106f0  a_data: 'h76fb93a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha  a_opcode: 'h4  a_user: 'h1ba9c  d_param: 'h0  d_source: 'ha  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2176.688894 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 2.chip_sw_rv_core_ibex_lockstep_glitch.94911760091660888576562528394383855519897666227466393289948132566119991442374
    Line 405, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2914.525034 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2914.525034 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' has 1 failures:
- Test chip_csr_hw_reset has 1 failures.
  - 2.chip_csr_hw_reset.5352292110743693953677843663209549923778665252330684997749488356939073753555
    Line 220, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_csr_hw_reset/latest/run.log
```
      Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
  UVM_ERROR @ 1872.466428 us: (alert_esc_if.sv:202) [ASSERT FAILED] AlertKnown_A
  UVM_INFO @ 1872.466428 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32968) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

2.chip_csr_mem_rw_with_rand_reset.110266102862853503208187335767318899552174814924418007940969914128126720796335
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2475.579600 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32968) { a_addr: 'h105e4  a_data: 'hd159917f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h12  a_opcode: 'h4  a_user: 'h19eaa  d_param: 'h0  d_source: 'h12  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2475.579600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31914) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

3.chip_tl_errors.38649176546512097514044309699528632219365587375376367139020363619350218157449
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/3.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2025.609016 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31914) { a_addr: 'h1046c  a_data: 'h70bb5bf5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h4  a_user: 'h1bdcc  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2025.609016 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31882) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

3.chip_csr_mem_rw_with_rand_reset.22403021648116892058945598547987015074952244616896549872844440883123666204458
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/3.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 1863.180972 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31882) { a_addr: 'h10548  a_data: 'h5617e50e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h21  a_opcode: 'h4  a_user: 'h1aee1  d_param: 'h0  d_source: 'h21  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1863.180972 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(reset_cause == HwReq)' has 1 failures:
- Test chip_sw_sensor_ctrl_alert has 1 failures.
  - 4.chip_sw_sensor_ctrl_alert.102463479626912068515979613010408704021750943038092337127764311589611046779851
    Line 412, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/4.chip_sw_sensor_ctrl_alert/latest/run.log
```
      Offending '(reset_cause == HwReq)'
  UVM_ERROR @ 3496.921164 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
  UVM_INFO @ 3496.921164 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@318004) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

4.chip_tl_errors.96306628983844228915151780587628365721347817653519616128351628825117155361068
Line 215, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/4.chip_tl_errors/latest/run.log

  UVM_ERROR @ 4079.508120 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@318004) { a_addr: 'h1051c  a_data: 'hcea2c4ae  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h31  a_opcode: 'h4  a_user: 'h1ae75  d_param: 'h0  d_source: 'h31  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4079.508120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31892) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

5.chip_tl_errors.113818546829193399645381765833723957790125680698228339912309333624797886179049
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/5.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2463.735083 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31892) { a_addr: 'h10688  a_data: 'h8470f0d9  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2  a_opcode: 'h4  a_user: 'h1babd  d_param: 'h0  d_source: 'h2  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2463.735083 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33224) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

5.chip_csr_mem_rw_with_rand_reset.52451122143124153045043729444521985876948676491381226437477542068486892741528
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/5.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2194.453438 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33224) { a_addr: 'h10604  a_data: 'h3cd9a20a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1d  a_opcode: 'h4  a_user: 'h19258  d_param: 'h0  d_source: 'h1d  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2194.453438 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35806) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

6.chip_tl_errors.103449266391366958781729173692369240566495449744346781262416768288685628184891
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/6.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2444.335897 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35806) { a_addr: 'h10450  a_data: 'hf726fb42  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h19  a_opcode: 'h4  a_user: 'h199b0  d_param: 'h0  d_source: 'h19  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2444.335897 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31976) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

6.chip_csr_mem_rw_with_rand_reset.29793833293357622533206069006657925615451985225260714765150453346948351697229
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/6.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 1720.690020 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31976) { a_addr: 'h106b8  a_data: 'heada9088  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3c  a_opcode: 'h4  a_user: 'h186b1  d_param: 'h0  d_source: 'h3c  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1720.690020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32234) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

7.chip_tl_errors.50598380220993688858098540565675524209995272809327219983321534718655198146116
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/7.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2495.378812 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32234) { a_addr: 'h10678  a_data: 'h79ff3fa9  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3f  a_opcode: 'h4  a_user: 'h19ea2  d_param: 'h0  d_source: 'h3f  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2495.378812 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32694) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

8.chip_tl_errors.53093479213599898058407670367717921138734634395453606981842573556676475981348
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/8.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2312.136749 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32694) { a_addr: 'h10350  a_data: 'hbace16f4  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h5  a_opcode: 'h4  a_user: 'h18688  d_param: 'h0  d_source: 'h5  d_data: 'h13  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd7d  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2312.136749 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34854) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

9.chip_tl_errors.95021385870789736611990873716365613868701085365075118076559382944779657504206
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/9.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2343.321632 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34854) { a_addr: 'h106b4  a_data: 'hc56e4ccb  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h30  a_opcode: 'h4  a_user: 'h19ea4  d_param: 'h0  d_source: 'h30  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2343.321632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46188) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

10.chip_tl_errors.2424876698282718084383955819842964541618230200378422831308998028430293189661
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/10.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2771.909592 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46188) { a_addr: 'h106c4  a_data: 'h66d755c0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hb  a_opcode: 'h4  a_user: 'h18a40  d_param: 'h0  d_source: 'hb  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2771.909592 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37778) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

11.chip_tl_errors.111246347613258438589677331409373324062047176510695124070704470163359700006487
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/11.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2302.110690 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37778) { a_addr: 'h10540  a_data: 'ha49031a5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2  a_opcode: 'h4  a_user: 'h1ba02  d_param: 'h0  d_source: 'h2  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2302.110690 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36622) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

11.chip_csr_mem_rw_with_rand_reset.4313754548298001352469458879996960091114754624901648420167504988138625800139
Line 223, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/11.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2365.558325 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36622) { a_addr: 'hda4  a_data: 'h84b3a490  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h1  a_user: 'h27f1f  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2365.558325 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@131492) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

12.chip_tl_errors.70075678335042795779411260424260078678123783119653685915309972681940472800700
Line 215, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/12.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2495.243089 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@131492) { a_addr: 'h10450  a_data: 'h86cb4bad  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1f  a_opcode: 'h4  a_user: 'h199b6  d_param: 'h0  d_source: 'h1f  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2495.243089 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@212960) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

12.chip_csr_mem_rw_with_rand_reset.58626339414353627048271285949619822867753458788055450493125366838089436853356
Line 239, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/12.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 6776.116520 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@212960) { a_addr: 'h10704  a_data: 'h9a66b17a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3b  a_opcode: 'h4  a_user: 'h19574  d_param: 'h0  d_source: 'h3b  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 6776.116520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34814) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

13.chip_tl_errors.21933418405151524794872247166896267310579248630851775204018832625374252705717
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/13.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2598.922605 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34814) { a_addr: 'h10374  a_data: 'h6c9f5b14  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h14  a_opcode: 'h4  a_user: 'h19286  d_param: 'h0  d_source: 'h14  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2598.922605 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32130) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

14.chip_tl_errors.20800193129791114248651971378722982228194889524178619766031316918649427113549
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/14.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2109.613768 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32130) { a_addr: 'h10350  a_data: 'hca8a6413  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h13  a_opcode: 'h4  a_user: 'h186c7  d_param: 'h0  d_source: 'h13  d_data: 'h13  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd7d  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2109.613768 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36430) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

14.chip_csr_mem_rw_with_rand_reset.87586212843881035413964383989382062673645144737750191517437424034972858548941
Line 223, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/14.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2587.508239 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36430) { a_addr: 'h10b4  a_data: 'h702acb51  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h35  a_opcode: 'h1  a_user: 'h261ca  d_param: 'h0  d_source: 'h35  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2587.508239 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32566) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

15.chip_csr_mem_rw_with_rand_reset.103763390000589250210152368273754113414246562415637704575915552793955248151572
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/15.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 3082.021035 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32566) { a_addr: 'h10594  a_data: 'h56efe8e6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3d  a_opcode: 'h4  a_user: 'h18a0b  d_param: 'h0  d_source: 'h3d  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3082.021035 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@40030) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

16.chip_tl_errors.48885592993868931559489055378435517118565086764866704382428206031107093860661
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/16.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2713.945996 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@40030) { a_addr: 'h10614  a_data: 'h4134ab07  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2d  a_opcode: 'h4  a_user: 'h1b697  d_param: 'h0  d_source: 'h2d  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2713.945996 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@137804) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

17.chip_tl_errors.12988384241999824804262652020833855018640072125847921461881399447115035761731
Line 215, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/17.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3140.701844 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@137804) { a_addr: 'h10608  a_data: 'hc968d8ca  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h5  a_opcode: 'h4  a_user: 'h18a4d  d_param: 'h0  d_source: 'h5  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3140.701844 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@216684) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

17.chip_csr_mem_rw_with_rand_reset.1945283407623094699290344297751200610296591674109030249914575739694365500162
Line 239, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/17.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 5875.844532 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@216684) { a_addr: 'h10778  a_data: 'h9481a976  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hd  a_opcode: 'h4  a_user: 'h199d1  d_param: 'h0  d_source: 'hd  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5875.844532 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34020) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

18.chip_tl_errors.464140877786913640056649522239029669285626816160999166926044130194408506285
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/18.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2301.049585 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34020) { a_addr: 'h104c8  a_data: 'h700b5873  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h29  a_opcode: 'h4  a_user: 'h19932  d_param: 'h0  d_source: 'h29  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2301.049585 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37138) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

19.chip_tl_errors.101533072460602675831632805956840718781927456448275063354231427470852125442607
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/19.chip_tl_errors/latest/run.log

  UVM_ERROR @ 1886.101364 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37138) { a_addr: 'h105ac  a_data: 'hed7c6a38  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h26  a_opcode: 'h4  a_user: 'h1a2c6  d_param: 'h0  d_source: 'h26  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1886.101364 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32054) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

19.chip_csr_mem_rw_with_rand_reset.64268912653114329989445759728882118204382438346665385774689826856965502877540
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/19.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 1794.558330 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32054) { a_addr: 'h10720  a_data: 'he9f9aba1  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2  a_opcode: 'h4  a_user: 'h1813f  d_param: 'h0  d_source: 'h2  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1794.558330 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33866) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

20.chip_tl_errors.61201376219685899234575746135898281176693605348351889441889872839677182403640
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/20.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2452.487553 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33866) { a_addr: 'h10554  a_data: 'h3e99879a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h31  a_opcode: 'h4  a_user: 'h19250  d_param: 'h0  d_source: 'h31  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2452.487553 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35348) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

21.chip_tl_errors.74484043806495960735709971473523536863111067061589508651091744173201658382749
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/21.chip_tl_errors/latest/run.log

  UVM_ERROR @ 1970.270307 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35348) { a_addr: 'h10400  a_data: 'h2507af35  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h37  a_opcode: 'h4  a_user: 'h195c6  d_param: 'h0  d_source: 'h37  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1970.270307 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38984) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

22.chip_tl_errors.49145749755642957939887877003823375611900380432830183166057387630283650101959
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/22.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2581.546875 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38984) { a_addr: 'h10554  a_data: 'hcfdb471e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'he  a_opcode: 'h4  a_user: 'h19262  d_param: 'h0  d_source: 'he  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2581.546875 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@278400) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

23.chip_tl_errors.64841286253032287241895761991231290416658359457868005393987392368091594479467
Line 215, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/23.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3964.431149 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@278400) { a_addr: 'h10548  a_data: 'h9d349ae3  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h26  a_opcode: 'h4  a_user: 'h1aeef  d_param: 'h0  d_source: 'h26  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3964.431149 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32136) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

24.chip_tl_errors.105977278804167398699364727951342128136631614228007967288471220434895463002210
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/24.chip_tl_errors/latest/run.log

  UVM_ERROR @ 1820.712712 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32136) { a_addr: 'h10424  a_data: 'he98229f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3c  a_opcode: 'h4  a_user: 'h181ed  d_param: 'h0  d_source: 'h3c  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1820.712712 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@233576) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

25.chip_tl_errors.28252512067688217159442882692410752121228025198850484110697210098842365679943
Line 215, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/25.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3431.339660 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@233576) { a_addr: 'h105b8  a_data: 'h5f6871fc  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h39  a_opcode: 'h4  a_user: 'h18aa1  d_param: 'h0  d_source: 'h39  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3431.339660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36314) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

26.chip_tl_errors.65470230003394378468114110102119786001325008030354657775337548159317875441159
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/26.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2019.450876 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36314) { a_addr: 'h10450  a_data: 'h2d01c781  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h32  a_opcode: 'h4  a_user: 'h199fc  d_param: 'h0  d_source: 'h32  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2019.450876 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34206) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

27.chip_tl_errors.70279345562334765319772966352135796042534197226529911977745640429547034669462
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/27.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2221.045896 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34206) { a_addr: 'h10494  a_data: 'h7f89eed6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha  a_opcode: 'h4  a_user: 'h18d42  d_param: 'h0  d_source: 'ha  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2221.045896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31934) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

28.chip_tl_errors.62191185184051051183885277327973301356221717168269533292610819458224920903688
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/28.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2811.042630 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31934) { a_addr: 'h104bc  a_data: 'hbee93150  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h8  a_opcode: 'h4  a_user: 'h1812a  d_param: 'h0  d_source: 'h8  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2811.042630 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37368) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

29.chip_tl_errors.35362600176863258005743687864799777920265782498652880159297530111534911219153
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/29.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2588.731480 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37368) { a_addr: 'h106ec  a_data: 'h6d376df7  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1a  a_opcode: 'h4  a_user: 'h1861f  d_param: 'h0  d_source: 'h1a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2588.731480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---