ADC_CTRL Simulation Results

Sunday November 09 2025 00:10:08 UTC

GitHub Revision: 35f91f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	21.680s	6.055ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	4.860s	1.314ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.800s	528.767us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.309m	52.239ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	6.150s	1.266ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.910s	547.125us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.800s	528.767us	20	20	100.00
		adc_ctrl_csr_aliasing	6.150s	1.266ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.879m	497.592ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	18.971m	492.921ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	22.754m	491.808ms	49	50	98.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	22.597m	495.490ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	23.529m	660.995ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.316m	619.156ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	17.575m	512.289ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	21.137m	542.217ms	30	50	60.00
V2	poweron_counter	adc_ctrl_poweron_counter	17.680s	5.308ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	2.434m	46.321ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	5.664m	140.211ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	57.955m	3.026s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	2.720s	534.019us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	2.350s	528.739us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	4.530s	544.822us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	4.530s	544.822us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	4.860s	1.314ms	5	5	100.00
		adc_ctrl_csr_rw	2.800s	528.767us	20	20	100.00
		adc_ctrl_csr_aliasing	6.150s	1.266ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	25.100s	5.292ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	4.860s	1.314ms	5	5	100.00
		adc_ctrl_csr_rw	2.800s	528.767us	20	20	100.00
		adc_ctrl_csr_aliasing	6.150s	1.266ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	25.100s	5.292ms	20	20	100.00
V2		TOTAL			719	740	97.16
V2S	tl_intg_err	adc_ctrl_sec_cm	11.820s	7.612ms	5	5	100.00
		adc_ctrl_tl_intg_err	28.150s	8.254ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	28.150s	8.254ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	14.671m	10.000s	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			896	920	97.39

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 15 failures:
  • Test adc_ctrl_clock_gating has 12 failures.

    • 0.adc_ctrl_clock_gating.33518638019771712922396536798501019948828511922732757061607146528831442204574
      Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

        UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 5.adc_ctrl_clock_gating.93989986702323536609771572447809971048228336421241060384512352854605136549175
      Line 165, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/5.adc_ctrl_clock_gating/latest/run.log

        UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 10 more failures.

  • Test adc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 31.adc_ctrl_stress_all_with_rand_reset.104080960324009393822772995290672762670261602199353451389318163418059611118245
      Line 256, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/31.adc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 41.adc_ctrl_stress_all_with_rand_reset.62238145490404329359165093512685250975985996011622905811605039070737467788378
      Line 231, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/41.adc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 7 failures:
  • Test adc_ctrl_clock_gating has 7 failures.

    • 1.adc_ctrl_clock_gating.36592446182532320239798190379446636274891812646924132680725070372439618091726
      Line 165, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/1.adc_ctrl_clock_gating/latest/run.log

        UVM_ERROR @ 191617455407 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 191617455407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 13.adc_ctrl_clock_gating.33827464372678417267579353966067036227752969565227787451200095366928838040591
      Line 165, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/13.adc_ctrl_clock_gating/latest/run.log

        UVM_ERROR @ 183043584140 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 183043584140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 5 more failures.

• UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 2 failures:

  • Test adc_ctrl_clock_gating has 1 failures.

    • 45.adc_ctrl_clock_gating.94723047800575901411228022740442382104431110021651169530116970425435605965645
      Line 182, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/45.adc_ctrl_clock_gating/latest/run.log

        UVM_ERROR @ 479565943870 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
        UVM_INFO @ 479565943870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test adc_ctrl_filters_interrupt has 1 failures.

    • 49.adc_ctrl_filters_interrupt.24383993507235612759039422513915576071794028102861337097668732174303931657227
      Line 180, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/49.adc_ctrl_filters_interrupt/latest/run.log

        UVM_ERROR @ 499570096696 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
        UVM_INFO @ 499570096696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---