AES/MASKED Simulation Results

Sunday November 09 2025 00:10:08 UTC

GitHub Revision: `35f91f3`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	92.458us	1	1	100.00
V1	smoke	aes_smoke	10.000s	1.488ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	101.946us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	59.350us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	12.000s	688.790us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	165.415us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	59.804us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	59.350us	20	20	100.00
		aes_csr_aliasing	4.000s	165.415us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	10.000s	1.488ms	50	50	100.00
		aes_config_error	7.000s	368.969us	50	50	100.00
		aes_stress	49.000s	2.699ms	50	50	100.00
V2	key_length	aes_smoke	10.000s	1.488ms	50	50	100.00
		aes_config_error	7.000s	368.969us	50	50	100.00
		aes_stress	49.000s	2.699ms	50	50	100.00
V2	back2back	aes_stress	49.000s	2.699ms	50	50	100.00
		aes_b2b	24.000s	442.296us	50	50	100.00
V2	backpressure	aes_stress	49.000s	2.699ms	50	50	100.00
V2	multi_message	aes_smoke	10.000s	1.488ms	50	50	100.00
		aes_config_error	7.000s	368.969us	50	50	100.00
		aes_stress	49.000s	2.699ms	50	50	100.00
		aes_alert_reset	22.000s	1.433ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	243.550us	50	50	100.00
		aes_config_error	7.000s	368.969us	50	50	100.00
		aes_alert_reset	22.000s	1.433ms	50	50	100.00
V2	trigger_clear_test	aes_clear	17.000s	1.193ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	9.000s	388.718us	1	1	100.00
V2	reset_recovery	aes_alert_reset	22.000s	1.433ms	50	50	100.00
V2	stress	aes_stress	49.000s	2.699ms	50	50	100.00
V2	sideload	aes_stress	49.000s	2.699ms	50	50	100.00
		aes_sideload	41.000s	2.114ms	50	50	100.00
V2	deinitialization	aes_deinit	15.000s	1.661ms	50	50	100.00
V2	stress_all	aes_stress_all	1.017m	9.629ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	79.110us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	4.000s	130.050us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	4.000s	130.050us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	101.946us	5	5	100.00
		aes_csr_rw	4.000s	59.350us	20	20	100.00
		aes_csr_aliasing	4.000s	165.415us	5	5	100.00
		aes_same_csr_outstanding	4.000s	157.870us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	101.946us	5	5	100.00
		aes_csr_rw	4.000s	59.350us	20	20	100.00
		aes_csr_aliasing	4.000s	165.415us	5	5	100.00
		aes_same_csr_outstanding	4.000s	157.870us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	35.000s	1.918ms	50	50	100.00
V2S	fault_inject	aes_fi	6.000s	112.970us	50	50	100.00
		aes_control_fi	53.000s	10.014ms	283	300	94.33
		aes_cipher_fi	59.000s	10.002ms	338	350	96.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	112.030us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	112.030us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	112.030us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	112.030us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	9.000s	252.515us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	3.719ms	5	5	100.00
		aes_tl_intg_err	4.000s	181.943us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	4.000s	181.943us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	22.000s	1.433ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	112.030us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	10.000s	1.488ms	50	50	100.00
		aes_stress	49.000s	2.699ms	50	50	100.00
		aes_alert_reset	22.000s	1.433ms	50	50	100.00
		aes_core_fi	31.000s	10.015ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	112.030us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	9.000s	112.691us	50	50	100.00
		aes_stress	49.000s	2.699ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	49.000s	2.699ms	50	50	100.00
		aes_sideload	41.000s	2.114ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	9.000s	112.691us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	9.000s	112.691us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	9.000s	112.691us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	9.000s	112.691us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	9.000s	112.691us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	49.000s	2.699ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	49.000s	2.699ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	6.000s	112.970us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	6.000s	112.970us	50	50	100.00
		aes_control_fi	53.000s	10.014ms	283	300	94.33
		aes_cipher_fi	59.000s	10.002ms	338	350	96.57
		aes_ctr_fi	4.000s	68.559us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	6.000s	112.970us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	6.000s	112.970us	50	50	100.00
		aes_control_fi	53.000s	10.014ms	283	300	94.33
		aes_cipher_fi	59.000s	10.002ms	338	350	96.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	59.000s	10.002ms	338	350	96.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	6.000s	112.970us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	6.000s	112.970us	50	50	100.00
		aes_control_fi	53.000s	10.014ms	283	300	94.33
		aes_ctr_fi	4.000s	68.559us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	6.000s	112.970us	50	50	100.00
		aes_control_fi	53.000s	10.014ms	283	300	94.33
		aes_cipher_fi	59.000s	10.002ms	338	350	96.57
		aes_ctr_fi	4.000s	68.559us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	22.000s	1.433ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	6.000s	112.970us	50	50	100.00
		aes_control_fi	53.000s	10.014ms	283	300	94.33
		aes_cipher_fi	59.000s	10.002ms	338	350	96.57
		aes_ctr_fi	4.000s	68.559us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	6.000s	112.970us	50	50	100.00
		aes_control_fi	53.000s	10.014ms	283	300	94.33
		aes_cipher_fi	59.000s	10.002ms	338	350	96.57
		aes_ctr_fi	4.000s	68.559us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	6.000s	112.970us	50	50	100.00
		aes_control_fi	53.000s	10.014ms	283	300	94.33
		aes_ctr_fi	4.000s	68.559us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	6.000s	112.970us	50	50	100.00
		aes_control_fi	53.000s	10.014ms	283	300	94.33
		aes_cipher_fi	59.000s	10.002ms	338	350	96.57
V2S		TOTAL			954	985	96.85
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	27.000s	3.515ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1561	1602	97.44

Failure Buckets

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_cipher_fi has 12 failures.
  - 58.aes_cipher_fi.7823958532155371882867556566367627740428682570815612219319684120282480834417
    Line 146, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/58.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10002327349 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002327349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 64.aes_cipher_fi.9332300310457808286174247296088971421467115377045371946735969244878267160341
    Line 137, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/64.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011509741 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011509741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 10 more failures.
Job timed out after * minutes has 9 failures:
- Test aes_control_fi has 9 failures.
  - 29.aes_control_fi.22316501951710115903625797205542169543277907033591082422537848249250665193362
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/29.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 56.aes_control_fi.83311830333923724794799003686340767232509076694961204345232782345319836454321
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/56.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 7 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 25.aes_control_fi.87633201658000521019026197932079181992211644982028296693985754890733843073246
    Line 143, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/25.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10014026635 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014026635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 38.aes_control_fi.29936414921292758809063030584345388754283253013869772236686665637634465316473
    Line 134, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/38.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006578397 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006578397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.63862180738922022201415927626229799131304573725061292617334375293412234209744
Line 351, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3626907192 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3626907192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.23209131830870184147293371872618092071050601684402485686519206560704532967810
Line 182, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 249000472 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 249000472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 3 failures:
- Test aes_stress_all_with_rand_reset has 3 failures.
  - 3.aes_stress_all_with_rand_reset.87775918020194300378180801673857051090118289847346761432651796715603991059221
    Line 156, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 815323746 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 815323746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.aes_stress_all_with_rand_reset.1854252678920373113938767439649052919871677031280294255210227658875000448335
    Line 831, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3514983821 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 3514983821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 0.aes_core_fi.59628534398590324295618412049509242134020207768750012980644375373738327133542
    Line 149, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10017960760 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017960760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 52.aes_core_fi.37199825852471905137454804721115698110805548604130195889292769244298285078264
    Line 141, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/52.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015478612 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015478612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.12059847599856813827048829397014735235977162123843057430271620660432051013279
    Line 141, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 114808913 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 114808913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.17090652202408104219862260114069224818629289557447170138052139817128590605484
    Line 511, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 285490656 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 285490656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```