AES/UNMASKED Simulation Results

Sunday November 09 2025 00:10:08 UTC

GitHub Revision: `35f91f3`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	8.000s	83.152us	1	1	100.00
V1	smoke	aes_smoke	4.000s	98.644us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	173.557us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	99.674us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	5.304ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	617.669us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	6.000s	198.613us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	99.674us	20	20	100.00
		aes_csr_aliasing	4.000s	617.669us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	4.000s	98.644us	50	50	100.00
		aes_config_error	11.000s	645.025us	50	50	100.00
		aes_stress	4.000s	220.997us	50	50	100.00
V2	key_length	aes_smoke	4.000s	98.644us	50	50	100.00
		aes_config_error	11.000s	645.025us	50	50	100.00
		aes_stress	4.000s	220.997us	50	50	100.00
V2	back2back	aes_stress	4.000s	220.997us	50	50	100.00
		aes_b2b	8.000s	266.392us	50	50	100.00
V2	backpressure	aes_stress	4.000s	220.997us	50	50	100.00
V2	multi_message	aes_smoke	4.000s	98.644us	50	50	100.00
		aes_config_error	11.000s	645.025us	50	50	100.00
		aes_stress	4.000s	220.997us	50	50	100.00
		aes_alert_reset	10.000s	916.037us	50	50	100.00
V2	failure_test	aes_man_cfg_err	6.000s	144.631us	50	50	100.00
		aes_config_error	11.000s	645.025us	50	50	100.00
		aes_alert_reset	10.000s	916.037us	50	50	100.00
V2	trigger_clear_test	aes_clear	9.000s	274.854us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	9.000s	177.689us	1	1	100.00
V2	reset_recovery	aes_alert_reset	10.000s	916.037us	50	50	100.00
V2	stress	aes_stress	4.000s	220.997us	50	50	100.00
V2	sideload	aes_stress	4.000s	220.997us	50	50	100.00
		aes_sideload	7.000s	88.311us	50	50	100.00
V2	deinitialization	aes_deinit	7.000s	125.941us	50	50	100.00
V2	stress_all	aes_stress_all	1.050m	6.721ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	50.157us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	4.000s	152.189us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	4.000s	152.189us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	173.557us	5	5	100.00
		aes_csr_rw	3.000s	99.674us	20	20	100.00
		aes_csr_aliasing	4.000s	617.669us	5	5	100.00
		aes_same_csr_outstanding	3.000s	82.210us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	173.557us	5	5	100.00
		aes_csr_rw	3.000s	99.674us	20	20	100.00
		aes_csr_aliasing	4.000s	617.669us	5	5	100.00
		aes_same_csr_outstanding	3.000s	82.210us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	4.000s	275.111us	50	50	100.00
V2S	fault_inject	aes_fi	4.000s	102.036us	50	50	100.00
		aes_control_fi	59.000s	200.000ms	277	300	92.33
		aes_cipher_fi	42.000s	10.017ms	326	350	93.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	7.000s	86.495us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	7.000s	86.495us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	7.000s	86.495us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	7.000s	86.495us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	2.289ms	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	5.000s	413.524us	5	5	100.00
		aes_tl_intg_err	4.000s	214.344us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	4.000s	214.344us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	10.000s	916.037us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	7.000s	86.495us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	4.000s	98.644us	50	50	100.00
		aes_stress	4.000s	220.997us	50	50	100.00
		aes_alert_reset	10.000s	916.037us	50	50	100.00
		aes_core_fi	4.217m	10.009ms	61	70	87.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	7.000s	86.495us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	5.000s	87.898us	50	50	100.00
		aes_stress	4.000s	220.997us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	4.000s	220.997us	50	50	100.00
		aes_sideload	7.000s	88.311us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	87.898us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	87.898us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	87.898us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	87.898us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	87.898us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	4.000s	220.997us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	4.000s	220.997us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	4.000s	102.036us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	4.000s	102.036us	50	50	100.00
		aes_control_fi	59.000s	200.000ms	277	300	92.33
		aes_cipher_fi	42.000s	10.017ms	326	350	93.14
		aes_ctr_fi	8.000s	63.255us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	4.000s	102.036us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	4.000s	102.036us	50	50	100.00
		aes_control_fi	59.000s	200.000ms	277	300	92.33
		aes_cipher_fi	42.000s	10.017ms	326	350	93.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	42.000s	10.017ms	326	350	93.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	4.000s	102.036us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	4.000s	102.036us	50	50	100.00
		aes_control_fi	59.000s	200.000ms	277	300	92.33
		aes_ctr_fi	8.000s	63.255us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	4.000s	102.036us	50	50	100.00
		aes_control_fi	59.000s	200.000ms	277	300	92.33
		aes_cipher_fi	42.000s	10.017ms	326	350	93.14
		aes_ctr_fi	8.000s	63.255us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	10.000s	916.037us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	4.000s	102.036us	50	50	100.00
		aes_control_fi	59.000s	200.000ms	277	300	92.33
		aes_cipher_fi	42.000s	10.017ms	326	350	93.14
		aes_ctr_fi	8.000s	63.255us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	4.000s	102.036us	50	50	100.00
		aes_control_fi	59.000s	200.000ms	277	300	92.33
		aes_cipher_fi	42.000s	10.017ms	326	350	93.14
		aes_ctr_fi	8.000s	63.255us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	4.000s	102.036us	50	50	100.00
		aes_control_fi	59.000s	200.000ms	277	300	92.33
		aes_ctr_fi	8.000s	63.255us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	4.000s	102.036us	50	50	100.00
		aes_control_fi	59.000s	200.000ms	277	300	92.33
		aes_cipher_fi	42.000s	10.017ms	326	350	93.14
V2S		TOTAL			929	985	94.31
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	33.000s	1.372ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1536	1602	95.88

Failure Buckets

Job timed out after * minutes has 27 failures:
- Test aes_cipher_fi has 13 failures.
  - 12.aes_cipher_fi.113644810651952959790006155062672812951000173662323622086732680905300166311783
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/12.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 26.aes_cipher_fi.74126834979591316023175250168489565888951802321656395195153245345605110018558
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/26.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 11 more failures.
- Test aes_control_fi has 14 failures.
  - 14.aes_control_fi.27827323160774559844833852230593891297636323174271658200220596333606699815258
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/14.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 19.aes_control_fi.107095385660656517641516492166895910348952232315412528347838502009800988154037
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/19.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 12 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_cipher_fi has 11 failures.
  - 8.aes_cipher_fi.105030434169990880219657639274293043685599479350261848928363228442071928354024
    Line 145, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/8.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10018831921 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018831921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 28.aes_cipher_fi.22898106617359076472197273379524337238244749099809056853088370972261088119228
    Line 141, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/28.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10052683719 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10052683719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 16.aes_control_fi.30959791498190130876725344736166194110140058829794449838176964651696333221124
    Line 137, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10002656079 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002656079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 101.aes_control_fi.52881001695378076827354289810331344216057058223577909118805036653112647284010
    Line 146, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/101.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10041691926 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10041691926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.17435949504130844861174082950598549743273700053505141863427077102064751600664
Line 1765, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1372443992 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1372443992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.4460142490386891418482607342456346075899350403377749783145587652849907271043
Line 405, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 113903110 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 113903110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 5.aes_core_fi.92754440560731081855378791010512617156062447216574450388010340754366899366858
    Line 141, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/5.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011539603 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011539603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 33.aes_core_fi.64276302351674239361978823898604766780333395376892187391666256697387989738431
    Line 143, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/33.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10005454890 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005454890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 2.aes_core_fi.110578321091424002066564308321623754078592164991592031316667405455064822239911
    Line 136, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/2.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10020792539 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020792539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 22.aes_core_fi.17819855241754135055543466585880891478660060104682586470325581583227036485464
    Line 132, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/22.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012303368 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012303368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 4.aes_stress_all_with_rand_reset.29532642169807832089287313814377828934420494595809977769844588199080349940535
    Line 468, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 541327227 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 541327227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.aes_stress_all_with_rand_reset.8356785976574347540090237820805993351442580447106518376045028465787292736782
    Line 476, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 608301407 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 608301407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.52615957750329616338336018222449425573474809657553987488032689948108649455046
    Line 145, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  39449357 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  39449357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 32.aes_core_fi.48820555442968775183078932128108916809493405437666505677120193426980978583821
    Line 134, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/32.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10028354682 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0x69632e84, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 10028354682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 50.aes_core_fi.17799506707931717753006778817838404948348640797995889498200416918037830121498
    Line 136, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/50.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10029692537 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0x4638184, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10029692537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_control_fi has 1 failures.
  - 52.aes_control_fi.60177511646249324408871753176378475057769044949024148640162124777863818052783
    Line 137, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/52.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 61.aes_core_fi.1862114433895633634535983612314226481961446396748656916824621461729871554263
    Line 133, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/61.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009232104 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0x42c90984, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10009232104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```