CSRNG Simulation Results

Sunday November 09 2025 00:10:08 UTC

GitHub Revision: 35f91f3

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	20.000s	80.897us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	13.639us	5	5	100.00
V1	csr_rw	csrng_csr_rw	3.000s	40.751us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	1.017m	4.858ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	3.000s	78.591us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	382.110us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	3.000s	40.751us	20	20	100.00
		csrng_csr_aliasing	3.000s	78.591us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	22.000s	1.177ms	200	200	100.00
V2	alerts	csrng_alert	59.000s	5.424ms	500	500	100.00
V2	err	csrng_err	4.000s	55.410us	500	500	100.00
V2	cmds	csrng_cmds	10.333m	40.555ms	50	50	100.00
V2	life cycle	csrng_cmds	10.333m	40.555ms	50	50	100.00
V2	stress_all	csrng_stress_all	18.083m	52.562ms	49	50	98.00
V2	intr_test	csrng_intr_test	3.000s	45.084us	50	50	100.00
V2	alert_test	csrng_alert_test	18.000s	35.877us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	13.000s	460.258us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	13.000s	460.258us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	13.639us	5	5	100.00
		csrng_csr_rw	3.000s	40.751us	20	20	100.00
		csrng_csr_aliasing	3.000s	78.591us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	223.403us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	13.639us	5	5	100.00
		csrng_csr_rw	3.000s	40.751us	20	20	100.00
		csrng_csr_aliasing	3.000s	78.591us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	223.403us	20	20	100.00
V2		TOTAL			1439	1440	99.93
V2S	tl_intg_err	csrng_sec_cm	6.000s	633.969us	5	5	100.00
		csrng_tl_intg_err	20.000s	1.417ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	21.000s	13.909us	50	50	100.00
		csrng_csr_rw	3.000s	40.751us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	59.000s	5.424ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	18.083m	52.562ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	22.000s	1.177ms	200	200	100.00
		csrng_err	4.000s	55.410us	500	500	100.00
		csrng_sec_cm	6.000s	633.969us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	22.000s	1.177ms	200	200	100.00
		csrng_err	4.000s	55.410us	500	500	100.00
		csrng_sec_cm	6.000s	633.969us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	22.000s	1.177ms	200	200	100.00
		csrng_err	4.000s	55.410us	500	500	100.00
		csrng_sec_cm	6.000s	633.969us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	22.000s	1.177ms	200	200	100.00
		csrng_err	4.000s	55.410us	500	500	100.00
		csrng_sec_cm	6.000s	633.969us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	22.000s	1.177ms	200	200	100.00
		csrng_err	4.000s	55.410us	500	500	100.00
		csrng_sec_cm	6.000s	633.969us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	22.000s	1.177ms	200	200	100.00
		csrng_err	4.000s	55.410us	500	500	100.00
		csrng_sec_cm	6.000s	633.969us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	22.000s	1.177ms	200	200	100.00
		csrng_err	4.000s	55.410us	500	500	100.00
		csrng_sec_cm	6.000s	633.969us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	59.000s	5.424ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	22.000s	1.177ms	200	200	100.00
		csrng_err	4.000s	55.410us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	18.083m	52.562ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	59.000s	5.424ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	20.000s	1.417ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	22.000s	1.177ms	200	200	100.00
		csrng_err	4.000s	55.410us	500	500	100.00
		csrng_sec_cm	6.000s	633.969us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	22.000s	1.177ms	200	200	100.00
		csrng_err	4.000s	55.410us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	22.000s	1.177ms	200	200	100.00
		csrng_err	4.000s	55.410us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	22.000s	1.177ms	200	200	100.00
		csrng_err	4.000s	55.410us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	22.000s	1.177ms	200	200	100.00
		csrng_err	4.000s	55.410us	500	500	100.00
		csrng_sec_cm	6.000s	633.969us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	22.000s	1.177ms	200	200	100.00
		csrng_err	4.000s	55.410us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	5.983m	23.327ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			1629	1630	99.94

Failure Buckets

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
  • Test csrng_stress_all has 1 failures.

    • 35.csrng_stress_all.16193449175400867551405275852302907607234291127768809901383071585274613811677
      Line 175, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/35.csrng_stress_all/latest/run.log

        UVM_ERROR @ 10389506604 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 10389506604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---