EDN Simulation Results

Sunday November 09 2025 00:10:08 UTC

GitHub Revision: 35f91f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.240s	17.719us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.080s	71.904us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.150s	17.996us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.030s	264.570us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.540s	204.335us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.210s	166.220us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.150s	17.996us	20	20	100.00
		edn_csr_aliasing	1.540s	204.335us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.370m	9.072ms	300	300	100.00
V2	csrng_commands	edn_genbits	1.370m	9.072ms	300	300	100.00
V2	genbits	edn_genbits	1.370m	9.072ms	300	300	100.00
V2	interrupts	edn_intr	1.280s	31.030us	50	50	100.00
V2	alerts	edn_alert	1.690s	407.699us	200	200	100.00
V2	errs	edn_err	1.550s	56.326us	100	100	100.00
V2	disable	edn_disable	1.140s	40.159us	50	50	100.00
		edn_disable_auto_req_mode	1.630s	40.206us	50	50	100.00
V2	stress_all	edn_stress_all	5.590s	533.945us	50	50	100.00
V2	intr_test	edn_intr_test	1.180s	15.135us	50	50	100.00
V2	alert_test	edn_alert_test	1.430s	64.372us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.370s	126.951us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.370s	126.951us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.080s	71.904us	5	5	100.00
		edn_csr_rw	1.150s	17.996us	20	20	100.00
		edn_csr_aliasing	1.540s	204.335us	5	5	100.00
		edn_same_csr_outstanding	1.790s	161.971us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.080s	71.904us	5	5	100.00
		edn_csr_rw	1.150s	17.996us	20	20	100.00
		edn_csr_aliasing	1.540s	204.335us	5	5	100.00
		edn_same_csr_outstanding	1.790s	161.971us	20	20	100.00
V2		TOTAL			940	940	100.00
V2S	tl_intg_err	edn_sec_cm	4.840s	1.124ms	5	5	100.00
		edn_tl_intg_err	3.110s	116.645us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.060s	17.709us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.690s	407.699us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	4.840s	1.124ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	4.840s	1.124ms	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	4.840s	1.124ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	4.840s	1.124ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.690s	407.699us	200	200	100.00
		edn_sec_cm	4.840s	1.124ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.690s	407.699us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.110s	116.645us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	2.533h	10.000s	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			1109	1130	98.14

Failure Buckets

• Job timed out after * minutes has 20 failures:
  • Test edn_stress_all_with_rand_reset has 20 failures.

    • 2.edn_stress_all_with_rand_reset.87745404669484688641430155403497408266367054090802249011568978529323918273152
      Log /nightly/current_run/scratch/master/edn-sim-vcs/2.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • 5.edn_stress_all_with_rand_reset.93367640881762135443392807231950605135320085239989493274640459690273227534218
      Log /nightly/current_run/scratch/master/edn-sim-vcs/5.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • ... and 18 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test edn_stress_all_with_rand_reset has 1 failures.

    • 36.edn_stress_all_with_rand_reset.21936588029413987274480944435054425255611940634922493542113093504859790362171
      Line 287, in log /nightly/current_run/scratch/master/edn-sim-vcs/36.edn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---