HMAC Simulation Results

Sunday November 09 2025 00:10:08 UTC

GitHub Revision: 35f91f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 16.120s 3.990ms 10 10 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.190s 34.634us 5 5 100.00
V1 csr_rw hmac_csr_rw 1.100s 48.861us 20 20 100.00
V1 csr_bit_bash hmac_csr_bit_bash 8.120s 1.451ms 5 5 100.00
V1 csr_aliasing hmac_csr_aliasing 6.420s 1.006ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.390s 41.706us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.100s 48.861us 20 20 100.00
hmac_csr_aliasing 6.420s 1.006ms 5 5 100.00
V1 TOTAL 65 65 100.00
V2 long_msg hmac_long_msg 1.699m 35.614ms 10 10 100.00
V2 back_pressure hmac_back_pressure 1.495m 1.840ms 25 25 100.00
V2 test_vectors hmac_test_sha256_vectors 4.396m 12.837ms 30 30 100.00
hmac_test_sha384_vectors 9.117m 30.907ms 75 75 100.00
hmac_test_sha512_vectors 10.359m 93.486ms 75 75 100.00
hmac_test_hmac256_vectors 16.090s 287.272us 50 50 100.00
hmac_test_hmac384_vectors 21.130s 1.918ms 60 60 100.00
hmac_test_hmac512_vectors 18.980s 525.998us 75 75 100.00
V2 burst_wr hmac_burst_wr 42.840s 4.386ms 50 50 100.00
V2 datapath_stress hmac_datapath_stress 27.639m 8.035ms 10 10 100.00
V2 error hmac_error 1.365m 31.641ms 10 10 100.00
V2 wipe_secret hmac_wipe_secret 2.253m 10.797ms 10 10 100.00
V2 save_and_restore hmac_smoke 16.120s 3.990ms 10 10 100.00
hmac_long_msg 1.699m 35.614ms 10 10 100.00
hmac_back_pressure 1.495m 1.840ms 25 25 100.00
hmac_datapath_stress 27.639m 8.035ms 10 10 100.00
hmac_burst_wr 42.840s 4.386ms 50 50 100.00
hmac_stress_all 54.673m 32.780ms 50 50 100.00
V2 fifo_empty_status_interrupt hmac_smoke 16.120s 3.990ms 10 10 100.00
hmac_long_msg 1.699m 35.614ms 10 10 100.00
hmac_back_pressure 1.495m 1.840ms 25 25 100.00
hmac_datapath_stress 27.639m 8.035ms 10 10 100.00
hmac_wipe_secret 2.253m 10.797ms 10 10 100.00
hmac_test_sha256_vectors 4.396m 12.837ms 30 30 100.00
hmac_test_sha384_vectors 9.117m 30.907ms 75 75 100.00
hmac_test_sha512_vectors 10.359m 93.486ms 75 75 100.00
hmac_test_hmac256_vectors 16.090s 287.272us 50 50 100.00
hmac_test_hmac384_vectors 21.130s 1.918ms 60 60 100.00
hmac_test_hmac512_vectors 18.980s 525.998us 75 75 100.00
V2 wide_digest_configurable_key_length hmac_smoke 16.120s 3.990ms 10 10 100.00
hmac_long_msg 1.699m 35.614ms 10 10 100.00
hmac_back_pressure 1.495m 1.840ms 25 25 100.00
hmac_datapath_stress 27.639m 8.035ms 10 10 100.00
hmac_burst_wr 42.840s 4.386ms 50 50 100.00
hmac_error 1.365m 31.641ms 10 10 100.00
hmac_wipe_secret 2.253m 10.797ms 10 10 100.00
hmac_test_sha256_vectors 4.396m 12.837ms 30 30 100.00
hmac_test_sha384_vectors 9.117m 30.907ms 75 75 100.00
hmac_test_sha512_vectors 10.359m 93.486ms 75 75 100.00
hmac_test_hmac256_vectors 16.090s 287.272us 50 50 100.00
hmac_test_hmac384_vectors 21.130s 1.918ms 60 60 100.00
hmac_test_hmac512_vectors 18.980s 525.998us 75 75 100.00
hmac_stress_all 54.673m 32.780ms 50 50 100.00
V2 stress_all hmac_stress_all 54.673m 32.780ms 50 50 100.00
V2 alert_test hmac_alert_test 0.940s 17.211us 50 50 100.00
V2 intr_test hmac_intr_test 0.940s 15.958us 50 50 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.730s 1.003ms 20 20 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.730s 1.003ms 20 20 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.190s 34.634us 5 5 100.00
hmac_csr_rw 1.100s 48.861us 20 20 100.00
hmac_csr_aliasing 6.420s 1.006ms 5 5 100.00
hmac_same_csr_outstanding 3.020s 757.509us 20 20 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.190s 34.634us 5 5 100.00
hmac_csr_rw 1.100s 48.861us 20 20 100.00
hmac_csr_aliasing 6.420s 1.006ms 5 5 100.00
hmac_same_csr_outstanding 3.020s 757.509us 20 20 100.00
V2 TOTAL 670 670 100.00
V2S tl_intg_err hmac_sec_cm 1.540s 358.475us 5 5 100.00
hmac_tl_intg_err 5.110s 230.042us 20 20 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 5.110s 230.042us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 16.120s 3.990ms 10 10 100.00
V3 stress_reset hmac_stress_reset 6.800s 125.776us 25 25 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 6.821m 11.686ms 35 35 100.00
V3 TOTAL 60 60 100.00
Unmapped tests hmac_directed 0.910s 26.111us 1 1 100.00
TOTAL 821 821 100.00