KEYMGR Simulation Results

Sunday November 09 2025 00:10:08 UTC

GitHub Revision: `35f91f3`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	24.070s	1.984ms	48	50	96.00
V1	random	keymgr_random	51.740s	17.868ms	49	50	98.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.510s	106.762us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.570s	31.632us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	11.710s	4.638ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	10.020s	475.395us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.630s	32.294us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.570s	31.632us	20	20	100.00
		keymgr_csr_aliasing	10.020s	475.395us	5	5	100.00
V1		TOTAL			152	155	98.06
V2	cfgen_during_op	keymgr_cfg_regwen	38.030s	1.839ms	49	50	98.00
V2	sideload	keymgr_sideload	27.540s	2.299ms	50	50	100.00
		keymgr_sideload_kmac	31.440s	1.346ms	50	50	100.00
		keymgr_sideload_aes	50.340s	3.826ms	50	50	100.00
		keymgr_sideload_otbn	30.460s	5.323ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	17.090s	2.406ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	5.810s	152.096us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	7.670s	2.255ms	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	41.180s	21.521ms	48	50	96.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	28.520s	3.973ms	49	50	98.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	23.850s	2.199ms	49	50	98.00
V2	stress_all	keymgr_stress_all	5.436m	43.322ms	49	50	98.00
V2	intr_test	keymgr_intr_test	1.250s	15.344us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.380s	20.758us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.140s	116.482us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.140s	116.482us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.510s	106.762us	5	5	100.00
		keymgr_csr_rw	1.570s	31.632us	20	20	100.00
		keymgr_csr_aliasing	10.020s	475.395us	5	5	100.00
		keymgr_same_csr_outstanding	2.950s	429.610us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.510s	106.762us	5	5	100.00
		keymgr_csr_rw	1.570s	31.632us	20	20	100.00
		keymgr_csr_aliasing	10.020s	475.395us	5	5	100.00
		keymgr_same_csr_outstanding	2.950s	429.610us	20	20	100.00
V2		TOTAL			733	740	99.05
V2S	sec_cm_additional_check	keymgr_sec_cm	11.930s	619.306us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	11.930s	619.306us	5	5	100.00
		keymgr_tl_intg_err	8.630s	399.855us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.380s	317.056us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.380s	317.056us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.380s	317.056us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.380s	317.056us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.320s	1.149ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	11.930s	619.306us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	11.930s	619.306us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	8.630s	399.855us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.380s	317.056us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	38.030s	1.839ms	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	51.740s	17.868ms	49	50	98.00
		keymgr_csr_rw	1.570s	31.632us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	51.740s	17.868ms	49	50	98.00
		keymgr_csr_rw	1.570s	31.632us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	51.740s	17.868ms	49	50	98.00
		keymgr_csr_rw	1.570s	31.632us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	5.810s	152.096us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	28.520s	3.973ms	49	50	98.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	28.520s	3.973ms	49	50	98.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	51.740s	17.868ms	49	50	98.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	21.530s	1.061ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	11.930s	619.306us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	11.930s	619.306us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	11.930s	619.306us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	39.080s	10.357ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	5.810s	152.096us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	11.930s	619.306us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	11.930s	619.306us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	11.930s	619.306us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	39.080s	10.357ms	49	50	98.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	39.080s	10.357ms	49	50	98.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	11.930s	619.306us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	39.080s	10.357ms	49	50	98.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	11.930s	619.306us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	39.080s	10.357ms	49	50	98.00
V2S		TOTAL			164	165	99.39
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	21.110s	3.182ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			1077	1110	97.03

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
- Test keymgr_stress_all_with_rand_reset has 22 failures.
  - 0.keymgr_stress_all_with_rand_reset.30100328243434605896829372822030698305038800860755666805536185255293312990840
    Line 178, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 179753899 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 179753899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.keymgr_stress_all_with_rand_reset.5151153120526100572556423081670190481331281121407543331003674182172437831447
    Line 155, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 124281285 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 124281285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 20 more failures.

UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 9 failures:

Test keymgr_kmac_rsp_err has 1 failures.

7.keymgr_kmac_rsp_err.6256828511455860621543254692741458635598003987224986415768705488343516701380
Line 634, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/7.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  71571967 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  71571967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_sw_invalid_input has 2 failures.

14.keymgr_sw_invalid_input.40027430262098967430224887936340137456069059785255228672486726527800367975200
Line 102, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/14.keymgr_sw_invalid_input/latest/run.log

  UVM_ERROR @   5981605 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @   5981605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.keymgr_sw_invalid_input.14855547125134648759982350162975407294582706408274330997553407072274665178386
Line 229, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/34.keymgr_sw_invalid_input/latest/run.log

  UVM_ERROR @  12747931 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  12747931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_hwsw_invalid_input has 1 failures.

14.keymgr_hwsw_invalid_input.48274516595130801216999616078849850000338409469534238943035239077815151859924
Line 350, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/14.keymgr_hwsw_invalid_input/latest/run.log

  UVM_ERROR @  48468510 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  48468510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_smoke has 2 failures.

17.keymgr_smoke.89333604881602319115401762094175959874015147590564701249356318455439433876325
Line 102, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/17.keymgr_smoke/latest/run.log

  UVM_ERROR @   9811439 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @   9811439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.keymgr_smoke.60325723622631849740042879989475388042104932194377220889736201936612931703821
Line 157, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/20.keymgr_smoke/latest/run.log

  UVM_ERROR @ 184677843 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 184677843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_stress_all has 1 failures.

27.keymgr_stress_all.30510894510855544038736322247875574339187200784773601953707839885439176423742
Line 491, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/27.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 2053392501 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 2053392501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more tests.

UVM_FATAL (keymgr_custom_cm_vseq.sv:40) [keymgr_custom_cm_vseq] wait timeout occurred! has 1 failures:
- Test keymgr_custom_cm has 1 failures.
  - 19.keymgr_custom_cm.70601743558382707329432724749880445357042896005167971272889676187050538597213
    Line 140, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/19.keymgr_custom_cm/latest/run.log
```
  UVM_FATAL @ 10356933117 ps: (keymgr_custom_cm_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.keymgr_custom_cm_vseq] wait timeout occurred!
  UVM_INFO @ 10356933117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data == gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.start` has 1 failures:
- Test keymgr_cfg_regwen has 1 failures.
  - 42.keymgr_cfg_regwen.109189244722246765917138702935595103640255233857102831780480040301726880153411
    Line 84, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/42.keymgr_cfg_regwen/latest/run.log
```
  UVM_ERROR @   3512810 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
  UVM_INFO @   3512810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```