KMAC/MASKED Simulation Results

Sunday November 09 2025 00:10:08 UTC

GitHub Revision: 35f91f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.391m	3.546ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.480s	26.840us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.590s	123.712us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.110s	995.922us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.520s	2.083ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.050s	486.897us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.590s	123.712us	20	20	100.00
		kmac_csr_aliasing	10.520s	2.083ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.140s	18.931us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.950s	36.406us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	56.953m	263.207ms	50	50	100.00
V2	burst_write	kmac_burst_write	23.468m	16.395ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	39.460m	95.958ms	5	5	100.00
		kmac_test_vectors_sha3_256	32.388m	59.245ms	5	5	100.00
		kmac_test_vectors_sha3_384	26.070m	300.616ms	5	5	100.00
		kmac_test_vectors_sha3_512	21.810m	242.647ms	5	5	100.00
		kmac_test_vectors_shake_128	42.363m	112.583ms	5	5	100.00
		kmac_test_vectors_shake_256	33.520m	74.544ms	5	5	100.00
		kmac_test_vectors_kmac	3.920s	242.085us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.220s	65.581us	5	5	100.00
V2	sideload	kmac_sideload	6.997m	6.902ms	50	50	100.00
V2	app	kmac_app	6.144m	120.122ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.364m	85.184ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.760m	68.779ms	48	50	96.00
V2	error	kmac_error	7.912m	18.187ms	50	50	100.00
V2	key_error	kmac_key_error	16.280s	6.060ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	9.110s	298.733us	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	57.260s	3.412ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	32.080s	2.952ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	48.460s	8.566ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	23.870s	577.572us	50	50	100.00
V2	stress_all	kmac_stress_all	41.785m	250.367ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.200s	11.658us	50	50	100.00
V2	alert_test	kmac_alert_test	1.400s	57.223us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.990s	299.409us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.990s	299.409us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.480s	26.840us	5	5	100.00
		kmac_csr_rw	1.590s	123.712us	20	20	100.00
		kmac_csr_aliasing	10.520s	2.083ms	5	5	100.00
		kmac_same_csr_outstanding	3.250s	439.810us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.480s	26.840us	5	5	100.00
		kmac_csr_rw	1.590s	123.712us	20	20	100.00
		kmac_csr_aliasing	10.520s	2.083ms	5	5	100.00
		kmac_same_csr_outstanding	3.250s	439.810us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.050s	153.390us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.050s	153.390us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.050s	153.390us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.050s	153.390us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.870s	225.932us	18	20	90.00
V2S	tl_intg_err	kmac_sec_cm	2.092m	33.184ms	5	5	100.00
		kmac_tl_intg_err	5.650s	290.485us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.650s	290.485us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	23.870s	577.572us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.391m	3.546ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.997m	6.902ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.050s	153.390us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.092m	33.184ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.092m	33.184ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.092m	33.184ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.391m	3.546ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	23.870s	577.572us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.092m	33.184ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.730m	64.769ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.391m	3.546ms	50	50	100.00
V2S		TOTAL			73	75	97.33
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.638m	7.270ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			934	940	99.36

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 2 failures:

  • Test kmac_stress_all_with_rand_reset has 2 failures.

    • 1.kmac_stress_all_with_rand_reset.41002399302553270576499290010101691209745291035476326559600724709962306909659
      Line 216, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5659878795 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 5659878795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.kmac_stress_all_with_rand_reset.83481343207338514934283766969741378860841679986229847917945368885795567988512
      Line 401, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7269953395 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 7269953395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:

  • Test kmac_entropy_refresh has 2 failures.

    • 6.kmac_entropy_refresh.50016187191665020640207805854475800122633005041005816507622560094483830494147
      Line 74, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_entropy_refresh/latest/run.log

        UVM_ERROR @  67033644 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @  67033644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 27.kmac_entropy_refresh.72201845875104459908739016409738383338137634216999994781112197883904213454897
      Line 83, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/27.kmac_entropy_refresh/latest/run.log

        UVM_ERROR @ 1471294978 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @ 1471294978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 2 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 2 failures.

    • 6.kmac_shadow_reg_errors_with_csr_rw.111513309875644427889763750773154357802987091314714281035885169181828694006125
      Line 116, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_ERROR @  20362200 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (3708206327 [0xdd06bcf7] vs 2771777530 [0xa535f7fa]) Regname: kmac_reg_block.prefix_4.prefix_0 reset value: 0x0
        UVM_INFO @  20362200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 10.kmac_shadow_reg_errors_with_csr_rw.115427780933228844953215084575192320174675114396068769434416930608927690662204
      Line 351, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_ERROR @ 103879598 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (401947038 [0x17f5399e] vs 118638927 [0x712494f]) Regname: kmac_reg_block.prefix_0.prefix_0 reset value: 0x0
        UVM_INFO @ 103879598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---