OTBN Simulation Results

Sunday November 09 2025 00:10:08 UTC

GitHub Revision: 35f91f3

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 10.000s 80.768us 0 1 0.00
V1 single_binary otbn_single 15.283m 3.143ms 0 100 0.00
V1 csr_hw_reset otbn_csr_hw_reset 10.000s 106.482us 5 5 100.00
V1 csr_rw otbn_csr_rw 8.000s 27.373us 20 20 100.00
V1 csr_bit_bash otbn_csr_bit_bash 12.000s 68.754us 5 5 100.00
V1 csr_aliasing otbn_csr_aliasing 8.000s 25.596us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 12.000s 126.474us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 8.000s 27.373us 20 20 100.00
otbn_csr_aliasing 8.000s 25.596us 5 5 100.00
V1 mem_walk otbn_mem_walk 46.000s 711.456us 5 5 100.00
V1 mem_partial_access otbn_mem_partial_access 28.000s 1.453ms 5 5 100.00
V1 TOTAL 65 166 39.16
V2 reset_recovery otbn_reset 45.000s 215.410us 0 10 0.00
V2 multi_error otbn_multi_err 56.000s 627.279us 0 1 0.00
V2 back_to_back otbn_multi 2.250m 523.583us 0 10 0.00
V2 stress_all otbn_stress_all 1.867m 415.325us 0 10 0.00
V2 lc_escalation otbn_escalate 29.000s 649.396us 16 60 26.67
V2 zero_state_err_urnd otbn_zero_state_err_urnd 8.000s 105.415us 3 5 60.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 20.000s 61.681us 0 10 0.00
V2 alert_test otbn_alert_test 8.000s 32.631us 50 50 100.00
V2 intr_test otbn_intr_test 10.000s 21.869us 50 50 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 12.000s 428.485us 20 20 100.00
V2 tl_d_illegal_access otbn_tl_errors 12.000s 428.485us 20 20 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 10.000s 106.482us 5 5 100.00
otbn_csr_rw 8.000s 27.373us 20 20 100.00
otbn_csr_aliasing 8.000s 25.596us 5 5 100.00
otbn_same_csr_outstanding 9.000s 20.545us 20 20 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 10.000s 106.482us 5 5 100.00
otbn_csr_rw 8.000s 27.373us 20 20 100.00
otbn_csr_aliasing 8.000s 25.596us 5 5 100.00
otbn_same_csr_outstanding 9.000s 20.545us 20 20 100.00
V2 TOTAL 159 246 64.63
V2S mem_integrity otbn_imem_err 10.000s 28.415us 1 10 10.00
otbn_dmem_err 13.000s 100.824us 0 15 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 24.000s 229.898us 0 5 0.00
otbn_controller_ispr_rdata_err 12.000s 41.145us 0 5 0.00
otbn_mac_bignum_acc_err 12.000s 69.017us 0 5 0.00
otbn_urnd_err 7.000s 13.765us 2 2 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 8.000s 23.432us 5 5 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 14.000s 10.012ms 0 2 0.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 10.000s 29.795us 7 10 70.00
V2S tl_intg_err otbn_sec_cm 4.017m 2.157ms 3 5 60.00
otbn_tl_intg_err 1.650m 645.238us 20 20 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 47.000s 200.205us 19 20 95.00
V2S prim_fsm_check otbn_sec_cm 4.017m 2.157ms 3 5 60.00
V2S prim_count_check otbn_sec_cm 4.017m 2.157ms 3 5 60.00
V2S sec_cm_mem_scramble otbn_smoke 10.000s 80.768us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 13.000s 100.824us 0 15 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 10.000s 28.415us 1 10 10.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 1.650m 645.238us 20 20 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 29.000s 649.396us 16 60 26.67
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 10.000s 28.415us 1 10 10.00
otbn_dmem_err 13.000s 100.824us 0 15 0.00
otbn_zero_state_err_urnd 8.000s 105.415us 3 5 60.00
otbn_illegal_mem_acc 8.000s 23.432us 5 5 100.00
otbn_sec_cm 4.017m 2.157ms 3 5 60.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 4.017m 2.157ms 3 5 60.00
V2S sec_cm_scramble_key_sideload otbn_single 15.283m 3.143ms 0 100 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 10.000s 28.415us 1 10 10.00
otbn_dmem_err 13.000s 100.824us 0 15 0.00
otbn_zero_state_err_urnd 8.000s 105.415us 3 5 60.00
otbn_illegal_mem_acc 8.000s 23.432us 5 5 100.00
otbn_sec_cm 4.017m 2.157ms 3 5 60.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 4.017m 2.157ms 3 5 60.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 29.000s 649.396us 16 60 26.67
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 10.000s 28.415us 1 10 10.00
otbn_dmem_err 13.000s 100.824us 0 15 0.00
otbn_zero_state_err_urnd 8.000s 105.415us 3 5 60.00
otbn_illegal_mem_acc 8.000s 23.432us 5 5 100.00
otbn_sec_cm 4.017m 2.157ms 3 5 60.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 4.017m 2.157ms 3 5 60.00
V2S sec_cm_data_reg_sw_sca otbn_single 15.283m 3.143ms 0 100 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 15.000s 49.670us 0 12 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 9.000s 27.370us 5 5 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 34.000s 134.733us 0 5 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 34.000s 134.733us 0 5 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 17.000s 64.202us 0 10 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 4.017m 2.157ms 3 5 60.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 4.017m 2.157ms 3 5 60.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 39.000s 135.699us 0 10 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 4.017m 2.157ms 3 5 60.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 4.017m 2.157ms 3 5 60.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 12.000s 130.402us 0 5 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 12.000s 130.402us 0 5 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 23.000s 63.365us 3 7 42.86
V2S sec_cm_data_mem_sec_wipe otbn_single 15.283m 3.143ms 0 100 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 15.283m 3.143ms 0 100 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 15.283m 3.143ms 0 100 0.00
V2S sec_cm_write_mem_integrity otbn_multi 2.250m 523.583us 0 10 0.00
V2S sec_cm_ctrl_flow_count otbn_single 15.283m 3.143ms 0 100 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 15.283m 3.143ms 0 100 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 17.000s 122.712us 0 5 0.00
V2S sec_cm_key_sideload otbn_single 15.283m 3.143ms 0 100 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 4.017m 2.157ms 3 5 60.00
V2S TOTAL 65 163 39.88
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 5.800m 1.296ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 289 585 49.40

Failure Buckets