35f91f3| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 34.000s | 18.485us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 2.000s | 16.468us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 2.000s | 26.539us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 5.000s | 584.242us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 2.000s | 17.531us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 2.000s | 54.517us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 2.000s | 26.539us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 2.000s | 17.531us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 59.133m | 600.000ms | 20 | 50 | 40.00 |
| V2 | cnt_rollover | cnt_rollover | 1.433m | 11.640ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 34.000s | 73.885us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 2.643h | 2.745s | 20 | 50 | 40.00 |
| V2 | alert_test | pattgen_alert_test | 30.000s | 15.198us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 2.000s | 40.309us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 4.000s | 95.010us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 4.000s | 95.010us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 2.000s | 16.468us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 2.000s | 26.539us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 2.000s | 17.531us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 2.000s | 26.703us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 2.000s | 16.468us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 2.000s | 26.539us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 2.000s | 17.531us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 2.000s | 26.703us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 280 | 340 | 82.35 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 3.000s | 306.875us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 30.000s | 39.344us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 3.000s | 306.875us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 2.483m | 21.418ms | 1 | 50 | 2.00 |
| V3 | TOTAL | 1 | 50 | 2.00 | |||
| Unmapped tests | pattgen_inactive_level | 4.367m | 10.018ms | 37 | 50 | 74.00 | |
| TOTAL | 448 | 570 | 78.60 |
UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 47 failures:
0.pattgen_stress_all_with_rand_reset.89284221405999861694607802592955246815078443897711781398971372086458376863541
Line 154, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3436478707 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 3436507930 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3436507930 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 3436907930 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
1.pattgen_stress_all_with_rand_reset.91297500654022351324307908451754796808652538533317825752899746475867248891771
Line 133, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 627513879 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 627525596 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 627525596 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 627925596 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
... and 45 more failures.
Job timed out after * minutes has 27 failures:
3.pattgen_stress_all.98706418351504976521547827852470838195520868279472611607119933236376471469732
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/3.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
5.pattgen_stress_all.102103026092153617259155246029982927015322733176262712906841079173191400508550
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/5.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
... and 13 more failures.
4.pattgen_perf.111104480979842438145961707158105208322623934431272329672214040808250257094290
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/4.pattgen_perf/latest/run.log
Job timed out after 60 minutes
14.pattgen_perf.87900473954120405329563820072249447059120943549804419221623652407856925415964
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/14.pattgen_perf/latest/run.log
Job timed out after 60 minutes
... and 10 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 18 failures:
2.pattgen_perf.48175240423149565735402816557645594881171295362540023684622547856582330958530
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/2.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.pattgen_perf.46733965287818774638465231664928197757375221212940009724947165491778851877109
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/3.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 16 more failures.
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 15 failures:
2.pattgen_stress_all.97298079189630190352595654989843041868919278677936654303284822724553608247505
Line 145, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/2.pattgen_stress_all/latest/run.log
UVM_ERROR @ 126172430877 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10878
6.pattgen_stress_all.85675130994333598698541128173243184641412875311724892301522787951585799388633
Line 136, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/6.pattgen_stress_all/latest/run.log
UVM_ERROR @ 1344936729736 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10188
... and 13 more failures.
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 2 failures:
11.pattgen_inactive_level.100557839373876079119331613340213658835812568324793185436785390564046298685236
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/11.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10008265753 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x1c0b37d0, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10008265753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.pattgen_inactive_level.43937384903921293376593682626933533389197536315133986784136995801808429837104
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/33.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10052679886 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xd11c110, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10052679886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:
19.pattgen_inactive_level.93657990615133866128910291297638380307530723035461393776527503955458675982243
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/19.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10113966292 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xc8dc9490, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10113966292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.pattgen_inactive_level.27532673624772268685179141777972585082338435318340107439674913590512563788303
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/22.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10013088454 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xeb1852d0, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10013088454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard] has 2 failures:
27.pattgen_stress_all_with_rand_reset.107880293569077468194315495018841708158524286284930010554307578058304343076032
Line 129, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/27.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 877798288 ps: (pattgen_scoreboard.sv:263) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
38.pattgen_stress_all_with_rand_reset.76523259280605692873174635832272821502598891178329280149529816439408267271196
Line 133, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/38.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1418777734 ps: (pattgen_scoreboard.sv:263) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 1 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:
32.pattgen_inactive_level.59119955735781210252320105022970537745706731706791753851726678691924049812371
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/32.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10011473644 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xcb4e8650, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10011473644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.pattgen_inactive_level.50300107961802855762572481284344270444666328627976567086217996789088571533852
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/47.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10017673032 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x9c96b690, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10017673032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
3.pattgen_inactive_level.19193327169112757708479856408120453494299891136498070484666066012272688942456
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/3.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10051182812 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x51152090, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10051182812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 1 failures:
8.pattgen_inactive_level.5064682517951197364515855006281267571239816786818792105233700502645820719345
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/8.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10016306212 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x4e910490, Comparison=CompareOpEq, exp_data=0x0, call_count=14)
UVM_INFO @ 10016306212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
24.pattgen_inactive_level.100054162277865186996553046092997540728500565282969655217778573342335949607348
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/24.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10002014864 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x60637d50, Comparison=CompareOpEq, exp_data=0x0, call_count=6)
UVM_INFO @ 10002014864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
26.pattgen_inactive_level.32186150767179998104516258436407000081761856892737050175015007245885969457796
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/26.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10029936457 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x9cd487d0, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
UVM_INFO @ 10029936457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
36.pattgen_inactive_level.102848285862972896748824945606223318111780766370277319145033960797843632376284
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/36.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10007493593 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x3d206a10, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10007493593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:
37.pattgen_inactive_level.63646294937358036884607438730746772234443844197396303731738419157583163077633
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/37.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10071783455 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x8873bed0, Comparison=CompareOpEq, exp_data=0x0, call_count=4)
UVM_INFO @ 10071783455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
49.pattgen_inactive_level.24303863536857683097555489040346793095670119942808719772439225891482467718081
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/49.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10017731867 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x84e99b10, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10017731867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---