35f91f3| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 7.600s | 141.112us | 2 | 2 | 100.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 7.150s | 569.583us | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 7.030s | 172.050us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 6.230s | 169.073us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 5.670s | 1.805ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 6.840s | 136.081us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 7.030s | 172.050us | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 5.670s | 1.805ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 4.180s | 374.969us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 5.140s | 1.070ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 67 | 67 | 100.00 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 7.420s | 636.961us | 2 | 2 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 26.770s | 13.188ms | 20 | 20 | 100.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 7.210s | 390.899us | 2 | 2 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 8.710s | 553.756us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 11.880s | 200.178us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 11.880s | 200.178us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 7.150s | 569.583us | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 7.030s | 172.050us | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 5.670s | 1.805ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 7.700s | 204.660us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 7.150s | 569.583us | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 7.030s | 172.050us | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 5.670s | 1.805ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 7.700s | 204.660us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 114 | 114 | 100.00 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 1.995m | 11.753ms | 15 | 20 | 75.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 33.660s | 863.143us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 4.375m | 3.220ms | 1 | 5 | 20.00 |
| rom_ctrl_tl_intg_err | 1.072m | 813.088us | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 4.375m | 3.220ms | 1 | 5 | 20.00 |
| V2S | prim_count_check | rom_ctrl_sec_cm | 4.375m | 3.220ms | 1 | 5 | 20.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.995m | 11.753ms | 15 | 20 | 75.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.995m | 11.753ms | 15 | 20 | 75.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 1.995m | 11.753ms | 15 | 20 | 75.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.995m | 11.753ms | 15 | 20 | 75.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.995m | 11.753ms | 15 | 20 | 75.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 4.375m | 3.220ms | 1 | 5 | 20.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 4.375m | 3.220ms | 1 | 5 | 20.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 7.600s | 141.112us | 2 | 2 | 100.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 7.600s | 141.112us | 2 | 2 | 100.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 7.600s | 141.112us | 2 | 2 | 100.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 1.072m | 813.088us | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 1.995m | 11.753ms | 15 | 20 | 75.00 |
| rom_ctrl_kmac_err_chk | 7.210s | 390.899us | 2 | 2 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 1.995m | 11.753ms | 15 | 20 | 75.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 1.995m | 11.753ms | 15 | 20 | 75.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 1.995m | 11.753ms | 15 | 20 | 75.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 33.660s | 863.143us | 20 | 20 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 4.375m | 3.220ms | 1 | 5 | 20.00 |
| V2S | TOTAL | 56 | 65 | 86.15 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 6.594m | 18.023ms | 20 | 20 | 100.00 |
| V3 | TOTAL | 20 | 20 | 100.00 | |||
| TOTAL | 257 | 266 | 96.62 |
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 5 failures:
2.rom_ctrl_corrupt_sig_fatal_chk.95587573492228224666546721567801026545330878184184723128830206174504878061114
Line 81, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_ERROR @ 523831266 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 523831266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.rom_ctrl_corrupt_sig_fatal_chk.41531933541270798495065824765309175863731510614886168870182215008491093399223
Line 96, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_ERROR @ 7171544188 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 7171544188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' has 2 failures:
3.rom_ctrl_sec_cm.17784798908844298586070436777705750075659260093138674502948258578937803617520
Line 109, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_sec_cm/latest/run.log
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 8599487ps failed at 8599487ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 13528122ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 13528122ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
4.rom_ctrl_sec_cm.37475224393711357238000026892942694971061386713349385635781462536849650036777
Line 105, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_sec_cm/latest/run.log
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 3927282ps failed at 3927282ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 11187283ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 11187283ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:
0.rom_ctrl_sec_cm.103600903504948500055293832261557099171414902698399101445326686173163593611518
Line 171, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 17718114ps failed at 17718114ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 17758114ps failed at 17758114ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:
1.rom_ctrl_sec_cm.64666013773741882563573445985381166417114928301478556103272402531086085201515
Line 1061, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 489156947ps failed at 489156947ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 489156947ps failed at 489156947ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'