ROM_CTRL/64KB Simulation Results

Sunday November 09 2025 00:10:08 UTC

GitHub Revision: 35f91f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	14.070s	1.010ms	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	21.040s	4.136ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	17.020s	3.814ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	11.760s	6.232ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	12.650s	291.709us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.270s	1.026ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	17.020s	3.814ms	20	20	100.00
		rom_ctrl_csr_aliasing	12.650s	291.709us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	12.550s	307.206us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	11.410s	953.553us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	13.480s	231.396us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	1.115m	4.179ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	24.980s	4.548ms	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	15.610s	3.968ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	17.470s	294.167us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	17.470s	294.167us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	21.040s	4.136ms	5	5	100.00
		rom_ctrl_csr_rw	17.020s	3.814ms	20	20	100.00
		rom_ctrl_csr_aliasing	12.650s	291.709us	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.430s	1.036ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	21.040s	4.136ms	5	5	100.00
		rom_ctrl_csr_rw	17.020s	3.814ms	20	20	100.00
		rom_ctrl_csr_aliasing	12.650s	291.709us	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.430s	1.036ms	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.957m	24.097ms	20	20	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.036m	2.093ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	9.621m	5.666ms	1	5	20.00
		rom_ctrl_tl_intg_err	2.826m	410.332us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	9.621m	5.666ms	1	5	20.00
V2S	prim_count_check	rom_ctrl_sec_cm	9.621m	5.666ms	1	5	20.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.957m	24.097ms	20	20	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.957m	24.097ms	20	20	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.957m	24.097ms	20	20	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.957m	24.097ms	20	20	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.957m	24.097ms	20	20	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	9.621m	5.666ms	1	5	20.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	9.621m	5.666ms	1	5	20.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	14.070s	1.010ms	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	14.070s	1.010ms	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	14.070s	1.010ms	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.826m	410.332us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.957m	24.097ms	20	20	100.00
		rom_ctrl_kmac_err_chk	24.980s	4.548ms	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.957m	24.097ms	20	20	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.957m	24.097ms	20	20	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.957m	24.097ms	20	20	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.036m	2.093ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	9.621m	5.666ms	1	5	20.00
V2S		TOTAL			61	65	93.85
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	6.338m	17.789ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			262	266	98.50

Failure Buckets

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 2 failures:

  • Test rom_ctrl_sec_cm has 2 failures.

    • 1.rom_ctrl_sec_cm.65343173838420873428630767379584810861557404227940943793752901847743992862252
      Line 297, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 16322455ps failed at 16322455ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 16322455ps failed at 16322455ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

    • 2.rom_ctrl_sec_cm.92829701734274737967640866844223670019070350565796419206483874327215097845444
      Line 300, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 54201396ps failed at 54201396ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 54201396ps failed at 54201396ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

• Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 3.rom_ctrl_sec_cm.682914759844040146742374792446004665369293996733048690389588371542495697026
      Line 235, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 157024465ps failed at 157024465ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 177107960ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 177107960ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
      

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 4.rom_ctrl_sec_cm.48580198991220808338785694702556754759209721333261865758626709002204679181826
      Line 245, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 57655319ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 57655319ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
        Starting assertion attempts at time 57655319ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))