RV_TIMER Simulation Results

Sunday November 09 2025 00:10:08 UTC

GitHub Revision: `35f91f3`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	2.280s	440.090us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.910s	21.709us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.940s	19.640us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.590s	570.845us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.200s	33.176us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.780s	28.700us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.940s	19.640us	20	20	100.00
		rv_timer_csr_aliasing	1.200s	33.176us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	12.050s	55.654ms	0	20	0.00
V2	disabled	rv_timer_disabled	5.760s	2.323ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	19.596m	6.331s	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	19.596m	6.331s	10	10	100.00
V2	stress	rv_timer_stress_all	13.350s	6.610ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	0.900s	41.676us	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.960s	28.791us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.090s	335.197us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.090s	335.197us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.910s	21.709us	5	5	100.00
		rv_timer_csr_rw	0.940s	19.640us	20	20	100.00
		rv_timer_csr_aliasing	1.200s	33.176us	5	5	100.00
		rv_timer_same_csr_outstanding	1.140s	105.130us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.910s	21.709us	5	5	100.00
		rv_timer_csr_rw	0.940s	19.640us	20	20	100.00
		rv_timer_csr_aliasing	1.200s	33.176us	5	5	100.00
		rv_timer_same_csr_outstanding	1.140s	105.130us	20	20	100.00
V2		TOTAL			190	210	90.48
V2S	tl_intg_err	rv_timer_sec_cm	1.440s	279.700us	5	5	100.00
		rv_timer_tl_intg_err	1.750s	222.268us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.750s	222.268us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	min_value	rv_timer_min	2.500s	750.435us	5	10	50.00
V3	max_value	rv_timer_max	2.250s	154.921us	1	10	10.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.086m	12.480ms	15	20	75.00
V3		TOTAL			21	40	52.50
		TOTAL			311	350	88.86

Failure Buckets

UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 25 failures:
- Test rv_timer_random_reset has 20 failures.
  - 0.rv_timer_random_reset.78021368690017255219323358752615642709902736278687821090320740188833519803694
    Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 306446796 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x8834d904) == 0x1
  UVM_INFO @ 306446796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_random_reset.52568566188120915718733101390402019468508336314490418966113263892514259932311
    Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 1243513897 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x70302504) == 0x1
  UVM_INFO @ 1243513897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 18 more failures.
- Test rv_timer_min has 5 failures.
  - 1.rv_timer_min.115431098083714268336106890140713015548159467438341793195932266598115349181803
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_min/latest/run.log
```
  UVM_FATAL @ 220146211 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x116c1704) == 0x1
  UVM_INFO @ 220146211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.rv_timer_min.89995157590561993594035054779060339031869198617753933398333355763746537841974
    Line 74, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/3.rv_timer_min/latest/run.log
```
  UVM_FATAL @ 126545398 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xca86bd04) == 0x1
  UVM_INFO @ 126545398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 9 failures:
- Test rv_timer_max has 9 failures.
  - 0.rv_timer_max.26849664649729310405914681474828674983331812635848532136502005696820641126409
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
```
  UVM_ERROR @ 154920908 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 154920908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_max.76267798717898056548892235774651404869666813118607427559404768544273662340042
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_max/latest/run.log
```
  UVM_ERROR @  83467813 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @  83467813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 3 failures:

Test rv_timer_stress_all_with_rand_reset has 3 failures.

1.rv_timer_stress_all_with_rand_reset.107724822092497381613685164918959130565215468853287695286637935228003155172475
Line 269, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3430975360 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3430975360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.rv_timer_stress_all_with_rand_reset.58671931326060871129471873272136898561598655406520781769978728216839747101701
Line 118, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/9.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 994635204 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 994635204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 2 failures:
- Test rv_timer_stress_all_with_rand_reset has 2 failures.
  - 3.rv_timer_stress_all_with_rand_reset.20767394838442501947344158856078160974346433072617029548720580491327617073341
    Line 117, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/3.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  98569375 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
  UVM_INFO @  98569375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 17.rv_timer_stress_all_with_rand_reset.56398883636477879501343573398782094101497799896437400825934604842981691398561
    Line 122, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/17.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1073853557 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
  UVM_INFO @ 1073853557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```