SPI_DEVICE/1R1W Simulation Results

Sunday November 09 2025 00:10:08 UTC

GitHub Revision: 35f91f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.995m	314.456ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.790s	40.597us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.920s	38.886us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	30.630s	4.756ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	18.020s	2.446ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.180s	534.091us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.920s	38.886us	20	20	100.00
		spi_device_csr_aliasing	18.020s	2.446ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.060s	34.327us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.570s	213.651us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.220s	57.927us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.110s	1.821us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.080s	3.554us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	5.140s	135.074us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	5.140s	135.074us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	32.320s	45.842ms	50	50	100.00
		spi_device_tpm_sts_read	1.430s	104.377us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	50.790s	35.935ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	32.360s	25.603ms	50	50	100.00
		spi_device_flash_all	5.033m	57.052ms	49	50	98.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	26.890s	67.131ms	50	50	100.00
		spi_device_flash_all	5.033m	57.052ms	49	50	98.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	26.890s	67.131ms	50	50	100.00
		spi_device_flash_all	5.033m	57.052ms	49	50	98.00
V2	cmd_info_slots	spi_device_flash_all	5.033m	57.052ms	49	50	98.00
V2	cmd_read_status	spi_device_intercept	24.650s	10.441ms	50	50	100.00
		spi_device_flash_all	5.033m	57.052ms	49	50	98.00
V2	cmd_read_jedec	spi_device_intercept	24.650s	10.441ms	50	50	100.00
		spi_device_flash_all	5.033m	57.052ms	49	50	98.00
V2	cmd_read_sfdp	spi_device_intercept	24.650s	10.441ms	50	50	100.00
		spi_device_flash_all	5.033m	57.052ms	49	50	98.00
V2	cmd_fast_read	spi_device_intercept	24.650s	10.441ms	50	50	100.00
		spi_device_flash_all	5.033m	57.052ms	49	50	98.00
V2	cmd_read_pipeline	spi_device_intercept	24.650s	10.441ms	50	50	100.00
		spi_device_flash_all	5.033m	57.052ms	49	50	98.00
V2	flash_cmd_upload	spi_device_upload	28.740s	20.613ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.909m	46.982ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.909m	46.982ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.909m	46.982ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.270m	24.626ms	50	50	100.00
		spi_device_read_buffer_direct	16.980s	4.782ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.909m	46.982ms	50	50	100.00
		spi_device_flash_all	5.033m	57.052ms	49	50	98.00
V2	quad_spi	spi_device_flash_all	5.033m	57.052ms	49	50	98.00
V2	dual_spi	spi_device_flash_all	5.033m	57.052ms	49	50	98.00
V2	4b_3b_feature	spi_device_cfg_cmd	17.190s	1.468ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	17.190s	1.468ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.995m	314.456ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.964m	255.071ms	50	50	100.00
V2	stress_all	spi_device_stress_all	16.504m	252.564ms	49	50	98.00
V2	alert_test	spi_device_alert_test	1.170s	22.308us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.170s	16.792us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.630s	478.481us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.630s	478.481us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.790s	40.597us	5	5	100.00
		spi_device_csr_rw	2.920s	38.886us	20	20	100.00
		spi_device_csr_aliasing	18.020s	2.446ms	5	5	100.00
		spi_device_same_csr_outstanding	4.570s	384.410us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.790s	40.597us	5	5	100.00
		spi_device_csr_rw	2.920s	38.886us	20	20	100.00
		spi_device_csr_aliasing	18.020s	2.446ms	5	5	100.00
		spi_device_same_csr_outstanding	4.570s	384.410us	20	20	100.00
V2		TOTAL			938	961	97.61
V2S	tl_intg_err	spi_device_sec_cm	1.760s	209.515us	5	5	100.00
		spi_device_tl_intg_err	17.180s	2.608ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	17.180s	2.608ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	22.973m	1.500s	49	50	98.00
		TOTAL			1127	1151	97.91

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 20 failures:

  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.112411241108081750537037945095547528039839329634331146767036488789718073235244
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1474662 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[79])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1474662 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1474662 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[975])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.95087739967282886410002426150093629521697818040860921636416659516225658770725
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @  19516046 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[83])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @  19516046 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @  19516046 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[979])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

• UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == gmv(csr) (* [] vs * []) CSR last_read_addr compare mismatch act * != exp *` has 2 failures:

  • Test spi_device_stress_all has 1 failures.

    • 0.spi_device_stress_all.36380058398616879178332832239858354329324864547042265832731689061087779790174
      Line 84, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_stress_all/latest/run.log

        UVM_ERROR @ 539268475 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (14380032 [0xdb6c00] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0xdb6c00 != exp 0x0
        UVM_INFO @ 555980868 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 0/10
        UVM_INFO @ 555980868 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 1/10
        UVM_INFO @ 641043171 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 3/7
        tl_ul_fuzzy_flash_status_q[i] = 0x24d2e0
      

  • Test spi_device_flash_all has 1 failures.

    • 3.spi_device_flash_all.7821577367007516773473170306218698499909561414465510444204168684969116388656
      Line 79, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/3.spi_device_flash_all/latest/run.log

        UVM_ERROR @ 1164909458 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (11028480 [0xa84800] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0xa84800 != exp 0x0
        tl_ul_fuzzy_flash_status_q[i] = 0x3b0258
        tl_ul_fuzzy_flash_status_q[i] = 0x3b0258
        tl_ul_fuzzy_flash_status_q[i] = 0x3b0258
        UVM_INFO @ 1572121458 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 1/12
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.204684737703809991071440220979452253440985469554711646140740244150035357087
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1022118 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x132800 [100110010100000000000] vs 0x0 [0])
        UVM_ERROR @   1068118 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe5ba63 [111001011011101001100011] vs 0x0 [0])
        UVM_ERROR @   1164118 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xedab96 [111011011010101110010110] vs 0x0 [0])
        UVM_ERROR @   1175118 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x64682e [11001000110100000101110] vs 0x0 [0])
        UVM_ERROR @   1215118 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf6cd07 [111101101100110100000111] vs 0x0 [0])
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 13.spi_device_flash_mode_ignore_cmds.2211736012235220750967180337144998720494191003870604751380286018798173444698
      Line 78, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/13.spi_device_flash_mode_ignore_cmds/latest/run.log

        UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---