SPI_DEVICE/2P Simulation Results

Sunday November 09 2025 00:10:08 UTC

GitHub Revision: 35f91f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	10.932m	90.809ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.740s	24.337us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.880s	38.051us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	26.820s	1.088ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	18.540s	1.143ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.930s	60.337us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.880s	38.051us	20	20	100.00
		spi_device_csr_aliasing	18.540s	1.143ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.040s	19.982us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.370s	26.878us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.210s	22.040us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.490s	26.776us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	1.000s	15.379us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	6.700s	215.141us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	6.700s	215.141us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	22.350s	6.148ms	50	50	100.00
		spi_device_tpm_sts_read	1.460s	424.385us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	54.540s	10.124ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	58.790s	57.546ms	50	50	100.00
		spi_device_flash_all	3.885m	143.711ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	37.580s	85.770ms	50	50	100.00
		spi_device_flash_all	3.885m	143.711ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	37.580s	85.770ms	50	50	100.00
		spi_device_flash_all	3.885m	143.711ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	3.885m	143.711ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	25.860s	2.385ms	50	50	100.00
		spi_device_flash_all	3.885m	143.711ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	25.860s	2.385ms	50	50	100.00
		spi_device_flash_all	3.885m	143.711ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	25.860s	2.385ms	50	50	100.00
		spi_device_flash_all	3.885m	143.711ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	25.860s	2.385ms	50	50	100.00
		spi_device_flash_all	3.885m	143.711ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	25.860s	2.385ms	50	50	100.00
		spi_device_flash_all	3.885m	143.711ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	23.210s	26.383ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.270m	36.625ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.270m	36.625ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.270m	36.625ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.491m	7.366ms	50	50	100.00
		spi_device_read_buffer_direct	18.940s	7.768ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.270m	36.625ms	50	50	100.00
		spi_device_flash_all	3.885m	143.711ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	3.885m	143.711ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	3.885m	143.711ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	13.540s	1.381ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	13.540s	1.381ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.932m	90.809ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	5.203m	474.942ms	50	50	100.00
V2	stress_all	spi_device_stress_all	15.671m	555.087ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.130s	26.221us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.140s	12.981us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.050s	360.999us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.050s	360.999us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.740s	24.337us	5	5	100.00
		spi_device_csr_rw	2.880s	38.051us	20	20	100.00
		spi_device_csr_aliasing	18.540s	1.143ms	5	5	100.00
		spi_device_same_csr_outstanding	4.120s	813.934us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.740s	24.337us	5	5	100.00
		spi_device_csr_rw	2.880s	38.051us	20	20	100.00
		spi_device_csr_aliasing	18.540s	1.143ms	5	5	100.00
		spi_device_same_csr_outstanding	4.120s	813.934us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.710s	540.684us	5	5	100.00
		spi_device_tl_intg_err	18.160s	1.799ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	18.160s	1.799ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	3.328m	118.581ms	49	50	98.00
		TOTAL			1150	1151	99.91

Failure Buckets

• UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == gmv(csr) (* [] vs * []) CSR last_read_addr compare mismatch act * != exp *` has 1 failures:
  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 9.spi_device_flash_mode_ignore_cmds.61870452097001066575393074408778530470717097912626799771000248499183549654625
      Line 87, in log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/9.spi_device_flash_mode_ignore_cmds/latest/run.log

        UVM_ERROR @ 646156165 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (11528192 [0xafe800] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0xafe800 != exp 0x0
        UVM_INFO @ 653512422 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 2/11
        UVM_INFO @ 653512422 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 3/11
        tl_ul_fuzzy_flash_status_q[i] = 0xed5274
        tl_ul_fuzzy_flash_status_q[i] = 0xed5274