SPI_HOST Simulation Results

Sunday November 09 2025 00:10:08 UTC

GitHub Revision: `35f91f3`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.983m	11.233ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	18.532us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	8.000s	44.570us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	485.396us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	48.159us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	26.730us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	8.000s	44.570us	20	20	100.00
		spi_host_csr_aliasing	3.000s	48.159us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	30.118us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	18.392us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	3.000s	88.460us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	23.000s	1.513ms	50	50	100.00
		spi_host_error_cmd	2.000s	53.294us	50	50	100.00
		spi_host_event	12.333m	25.350ms	50	50	100.00
V2	clock_rate	spi_host_speed	33.000s	10.042ms	49	50	98.00
V2	speed	spi_host_speed	33.000s	10.042ms	49	50	98.00
V2	chip_select_timing	spi_host_speed	33.000s	10.042ms	49	50	98.00
V2	sw_reset	spi_host_sw_reset	3.283m	7.426ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	21.829us	50	50	100.00
V2	cpol_cpha	spi_host_speed	33.000s	10.042ms	49	50	98.00
V2	full_cycle	spi_host_speed	33.000s	10.042ms	49	50	98.00
V2	duplex	spi_host_smoke	1.983m	11.233ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	1.983m	11.233ms	50	50	100.00
V2	stress_all	spi_host_stress_all	1.400m	9.060ms	50	50	100.00
V2	spien	spi_host_spien	3.583m	21.954ms	50	50	100.00
V2	stall	spi_host_status_stall	7.483m	181.623ms	48	50	96.00
V2	Idlecsbactive	spi_host_idlecsbactive	16.000s	5.644ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	23.000s	1.513ms	50	50	100.00
V2	alert_test	spi_host_alert_test	3.000s	183.039us	50	50	100.00
V2	intr_test	spi_host_intr_test	3.000s	19.905us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	9.000s	571.130us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	9.000s	571.130us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	18.532us	5	5	100.00
		spi_host_csr_rw	8.000s	44.570us	20	20	100.00
		spi_host_csr_aliasing	3.000s	48.159us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	109.022us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	18.532us	5	5	100.00
		spi_host_csr_rw	8.000s	44.570us	20	20	100.00
		spi_host_csr_aliasing	3.000s	48.159us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	109.022us	20	20	100.00
V2		TOTAL			687	690	99.57
V2S	tl_intg_err	spi_host_tl_intg_err	8.000s	98.487us	20	20	100.00
		spi_host_sec_cm	2.000s	129.625us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	8.000s	98.487us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	7.050m	11.675ms	10	10	100.00
		TOTAL			837	840	99.64

Failure Buckets

UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 1 failures:
- Test spi_host_speed has 1 failures.
  - 17.spi_host_speed.62356436750764089090071618531490926138868053346248301081668023394994949586364
    Line 270, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/17.spi_host_speed/latest/run.log
```
  UVM_FATAL @ 10041610141 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0x3218ff94, Comparison=CompareOpEq, exp_data=0x0, call_count=44
  UVM_INFO @ 10041610141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 17.spi_host_status_stall.15397277973837668587753694135914626618564805862043068472894386046271520727891
    Line 2019, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/17.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 53265493984 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 15000000ns spi_host_reg_block.status.active (addr=0x3000a714, Comparison=CompareOpEq, exp_data=0x0, call_count=656
  UVM_INFO @ 53265493984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed has 1 failures:

Test spi_host_status_stall has 1 failures.

48.spi_host_status_stall.10007770798002597894711101742066112624623615191338755032497586169670089912334
Line 4403, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/48.spi_host_status_stall/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 4525354124 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
  UVM_ERROR @ 4525354124 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time=4525354000 ps
  UVM_INFO @ 4525354124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---